chipreset
- if not (call si_iscoreup())
- if bustype is SI_BUS
call si_pci_setup() coremask= 1 << <coreindex> (does nothing on SoCs) (see: brcm/shared/siutils.c)
- goto chipinreset
- if bustype is SI_BUS
- if chipreset runs the first time for this device
call chipstatsupd
- for 0 ... 3 (for all tx queues)
- call dma_txreset() (see: brcm/shared/hnddma.c)
call gmac_macloopback with true
- wait 1 usec
- call dma_rxreset() with RX queue
call gmac_mf_cleanup (this clears the software multicast filter list)
chipinreset:
- call si_core_sflags() and store result in sflags
- if (chipid is 0x5357 or chipid is 0x4749) and chippkg is 10) or (chipid is 53572 and chippkg is 9)
- unset SISF_SW_ATTACHED in sflags
- if SISF_SW_ATTACHED is set in sflags
- set flagbits to SICF_SWCLKE
- if robo switch is present
- set SICF_SWRST bits in flagbits
- call si_core_reset() with flagbits
if corerev > 2
- Or Gmac Core reg clk_ctl_st with CS_ER
- wait for a max of 1000 usec and check every 10 usec if CS_ES is set in clk_ctl_st
- if chipid is 0x5357 or chipdid is 0x4749 or chipid is 53572
- set sw_type to PMU_CC1_SW_TYPE_EPHY | PMU_CC1_IF_TYPE_MII
- if nvram var et_swtype is available
- fetch et_swtype from nvram and store
- mask it with 0x0f
- shift it to the left by 4
- set sw_type to that value
- else if chipid is 0x5357 and chippkg is 9
- set sw_type to PMU_CC1_SW_TYPE_EPHYRMII
- else if (chipid is not 53572 and chippkg is 10) or (chipid is 53572 and chippkg is 9)
- set sw_type to PMU_CC1_IF_TYPE_RGMII|PMU_CC1_SW_TYPE_RGMII
- call si_pmu_chipcontrol() with sih, PMU_CHIPCTL1, (PMU_CC1_IF_TYPE_MASK|PMU_CC1_SW_TYPE_MASK) and sw_type (see: brcm/shared/hndpmu.c)
- if SISF_SW_ATTACHED is set in sflags and no robo switch is present
- cll si_core_cflags() with SICF_SWRST (see: brcm/shared/siutils.c)
call gmac_reset
call gmac_clearmib
- if corerev is 0x80000000
- or Gmac common reg phycontrol with PC_MTE
- else
- or Gmac Core reg phycontrol with PC_MTE
call gmac_miiconfig
call chipphyinit with phyaddr fetched in chipattach
- clear sw intstatus
gmac_miiconfig
- Read Gmac core reg devstatus into devstatus
- mask devstatus with DS_MM_MASK and shift it to the right by DS_MM_SHIFT
- If the result is 0 or 1
- if the user selected autospeed
call gmac_speed with 100MBit/Full
- else
call gmac_speed with selected speed
- if the user selected autospeed
gmac_clearmib
- if corerev == 0x80000000 (GMAC_4706B0_CORE_REV)
- return
- OR Gmac core Reg devcontrol with 0x00000010 (DC_MROR)
for all GMAC MIB registers
- read reg[i]
chipstatsupd
this reads all GMAC MIB registers and stores then in memory.