1. if not (call si_iscoreup())
    1. if bustype is SI_BUS
      1. call si_pci_setup() coremask= 1 << <coreindex> (does nothing on SoCs) (see: brcm/shared/siutils.c)

    2. goto chipinreset
  2. if chipreset runs the first time for this device
    1. call chipstatsupd

  3. for 0 ... 3 (for all tx queues)
    1. call dma_txreset() (see: brcm/shared/hnddma.c)
  4. call gmac_macloopback with true

  5. wait 1 usec
  6. call dma_rxreset() with RX queue
  7. call gmac_mf_cleanup (this clears the software multicast filter list)


  1. call si_core_sflags() and store result in sflags
  2. if (chipid is 0x5357 or chipid is 0x4749) and chippkg is 10) or (chipid is 53572 and chippkg is 9)
    1. unset SISF_SW_ATTACHED in sflags
  3. if SISF_SW_ATTACHED is set in sflags
    1. set flagbits to SICF_SWCLKE
    2. if robo switch is present
      1. set SICF_SWRST bits in flagbits
  4. call si_core_reset() with flagbits
  5. if corerev > 2

    1. Or Gmac Core reg clk_ctl_st with CS_ER
    2. wait for a max of 1000 usec and check every 10 usec if CS_ES is set in clk_ctl_st
  6. if chipid is 0x5357 or chipdid is 0x4749 or chipid is 53572
    1. set sw_type to PMU_CC1_SW_TYPE_EPHY | PMU_CC1_IF_TYPE_MII
    2. if nvram var et_swtype is available
      1. fetch et_swtype from nvram and store
      2. mask it with 0x0f
      3. shift it to the left by 4
      4. set sw_type to that value
    3. else if chipid is 0x5357 and chippkg is 9
      1. set sw_type to PMU_CC1_SW_TYPE_EPHYRMII
    4. else if (chipid is not 53572 and chippkg is 10) or (chipid is 53572 and chippkg is 9)
      1. set sw_type to PMU_CC1_IF_TYPE_RGMII|PMU_CC1_SW_TYPE_RGMII
    5. call si_pmu_chipcontrol() with sih, PMU_CHIPCTL1, (PMU_CC1_IF_TYPE_MASK|PMU_CC1_SW_TYPE_MASK) and sw_type (see: brcm/shared/hndpmu.c)
  7. if SISF_SW_ATTACHED is set in sflags and no robo switch is present
    1. cll si_core_cflags() with SICF_SWRST (see: brcm/shared/siutils.c)
  8. call gmac_reset

  9. call gmac_clearmib

  10. if corerev is 0x80000000
    1. or Gmac common reg phycontrol with PC_MTE
  11. else
    1. or Gmac Core reg phycontrol with PC_MTE
  12. call gmac_miiconfig

  13. call chipphyinit with phyaddr fetched in chipattach

  14. clear sw intstatus


  1. Read Gmac core reg devstatus into devstatus
  2. mask devstatus with DS_MM_MASK and shift it to the right by DS_MM_SHIFT
  3. If the result is 0 or 1
    1. if the user selected autospeed
      1. call gmac_speed with 100MBit/Full

    2. else
      1. call gmac_speed with selected speed


  1. if corerev == 0x80000000 (GMAC_4706B0_CORE_REV)
    1. return
  2. OR Gmac core Reg devcontrol with 0x00000010 (DC_MROR)
  3. for all GMAC MIB registers

    1. read reg[i]


Exported/Archived from the wiki to HTML on 2016-10-27