802.11/PHY/N/TxPwrCtrlSetup

N PHY TX Power Control Setup

Create 2 element s16 arrays a1, b0, and b1
Create 2 element u8 array idle
Create 2 element s8 array target
Create 64 element u32 array regval
If 802.11 core revision is 11 or 12
1. Set bit 1 << 21 in MAC control register
2. Do dummy read of MAC control register
3. Delay 1 usec
if phyhang_avoid is not zero
1. Call N PHY Stay In Carrier Search with argument 1 (enable)
Set bit 1 in PHY Register 0x122
If PHY Revision >= 3
1. Clear bit 1 << 15 in PHY Register 0x1E7
Otherwise
1. Set bit 1 << 15 in PHY Register 0x1E7
If 802.11 core revision is 11 or 12
1. Clear bit 1 << 21 in MAC control register
If SPROM Revision < 4
1. Set idle[0] to nphy_pwrctrl_info[0].idle_tssi_2g
2. Set idle[1] to nphy_pwrctrl_info[1].idle_tssi_2g
3. Set both elements of target to 52
4. Set both elements of a1 to -424
5. Set both elements of b0 to 5612
6. Set both elements of b1 to -1393
Otherwise
1. Call N PHY Get Channel Frequency Range with argument 0 and save result in chan_range
2. If chan_range is 0
  1. Set idle[0] to nphy_pwrctrl_info[0].idle_tssi_2g
  2. Set idle[1] to nphy_pwrctrl_info[1].idle_tssi_2g
  3. Set target[0] to nphy_pwrctrl_info[0].max_pwr_2g
  4. Set target[1] to nphy_pwrctrl_info[1].max_pwr_2g
  5. Set a1[0] to nphy_pwrctrl_info[0].pwrdet_2g_a1
  6. Set a1[1] to nphy_pwrctrl_info[1].pwrdet_2g_a1
  7. Set b0[0] to nphy_pwrctrl_info[0].pwrdet_2g_b0
  8. Set b0[1] to nphy_pwrctrl_info[1].pwrdet_2g_b0
  9. Set b1[1] to nphy_pwrctrl_info[0].pwrdet_2g_b1
  10. Set b1[1] to nphy_pwrctrl_info[1].pwrdet_2g_b1
3. Else if chan_range is 1
  1. Set idle[0] to nphy_pwrctrl_info[0].idle_tssi_5g
  2. Set idle[1] to nphy_pwrctrl_info[1].idle_tssi_5g
  3. Set target[0] to nphy_pwrctrl_info[0].max_pwr_5gl
  4. Set target[1] to nphy_pwrctrl_info[1].max_pwr_5gl
  5. Set a1[0] to nphy_pwrctrl_info[0].pwrdet_5gl_a1
  6. Set a1[1] to nphy_pwrctrl_info[1].pwrdet_5gl_a1
  7. Set b0[0] to nphy_pwrctrl_info[0].pwrdet_5gl_b0
  8. Set b0[1] to nphy_pwrctrl_info[1].pwrdet_5gl_b0
  9. Set b1[1] to nphy_pwrctrl_info[0].pwrdet_5gl_b1
  10. Set b1[1] to nphy_pwrctrl_info[1].pwrdet_5gl_b1
4. Else if chan_range is 2
  1. Set idle[0] to nphy_pwrctrl_info[0].idle_tssi_5g
  2. Set idle[1] to nphy_pwrctrl_info[1].idle_tssi_5g
  3. Set target[0] to nphy_pwrctrl_info[0].max_pwr_5gm
  4. Set target[1] to nphy_pwrctrl_info[1].max_pwr_5gm
  5. Set a1[0] to nphy_pwrctrl_info[0].pwrdet_5gm_a1
  6. Set a1[1] to nphy_pwrctrl_info[1].pwrdet_5gm_a1
  7. Set b0[0] to nphy_pwrctrl_info[0].pwrdet_5gm_b0
  8. Set b0[1] to nphy_pwrctrl_info[1].pwrdet_5gm_b0
  9. Set b1[1] to nphy_pwrctrl_info[0].pwrdet_5gm_b1
  10. Set b1[1] to nphy_pwrctrl_info[1].pwrdet_5gm_b1
5. Else if chan_range is 3
  1. Set idle[0] to nphy_pwrctrl_info[0].idle_tssi_5g
  2. Set idle[1] to nphy_pwrctrl_info[1].idle_tssi_5g
  3. Set target[0] to nphy_pwrctrl_info[0].max_pwr_5gh
  4. Set target[1] to nphy_pwrctrl_info[1].max_pwr_5gh
  5. Set a1[0] to nphy_pwrctrl_info[0].pwrdet_5gh_a1
  6. Set a1[1] to nphy_pwrctrl_info[1].pwrdet_5gh_a1
  7. Set b0[0] to nphy_pwrctrl_info[0].pwrdet_5gh_b0
  8. Set b0[1] to nphy_pwrctrl_info[1].pwrdet_5gh_b0
  9. Set b1[1] to nphy_pwrctrl_info[0].pwrdet_5gh_b1
  10. Set b1[1] to nphy_pwrctrl_info[1].pwrdet_5gh_b1
6. Otherwise
  1. Set idle[0] to nphy_pwrctrl_info[0].idle_tssi_2g
  2. Set idle[1] to nphy_pwrctrl_info[1].idle_tssi_2g
  3. Set both elements of target to 52 1, Set both elements of a1 to -424
  4. Set both elements of b0 to 5612
  5. Set both elements of b1 to -1393
Set target[0] to tx_power_max
Set target[1] to tx_power_max (Yes, they just overwrote the values set above!)
If PHY Revision >= 3
1. If SPROM FEM 2G TSSI POS
  1. Set bit 0x1 << 14) in PHY Register 0x1E9
2. If PHY Revision >= 7
  1. Loop for core equal 0, 1
    1. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)
      1. If this is a 2G channel
        Write 0xE to Radio Register (core == 0) ? 0x179 : 0x199
      2. Otherwise
        Write 0xC to Radio Register (core == 0) ? 0x179 : 0x199
3. Otherwise
  1. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)
    1. If this is a 5G channel
      1. Set tmp to 0xC
    2. Otherwise
      1. Set tmp to 0xE
    3. Write tmp to Radio Register 0x202D
    4. Write tmp to Radio Register 0x302D
  2. Otherwise
    1. Write 0x11 to Radio Register 0x202D
    2. Write 0x11 to Radio Register 0x302D
If 802.11 core revision is 11 or 12
1. Set bit 1 << 21 in MAC control register
2. Do dummy read of MAC control register
3. Delay 1 usec
If PHY Revision >= 7
1. Maskset PHY Register 0x1E7 with mask 0xFF80 and set with 0x19
Otherwise
1. Maskset PHY Register 0x1E7 with mask 0xFF80 and set with 0x40
If PHY Revision >= 7
1. Maskset PHY Register 0x222 with mask 0xFF00 and set with 0x19
Else if PHY Revision > 1
1. Maskset PHY Register 0x222 with mask 0xFF00 and set with 0x40
If 802.11 core revision is 11 or 12
1. Clear bit 1 << 21 in MAC control register
Write 0x3F0 to PHY Register 0x1E8
Write (1 << 15 | idle[1] << 8 | idle[0]) to PHY Register 0x1E9
Write (target[1] << 8 | target[0]) to PHY Register 0x1EA
Loop for id values of 0 and 1
1. Loop for index from 0 through 63 (inclusive)
  1. Set num to 8 * (16 * b0[id] + b1[id] * index)
  2. Set den to 32768 + a1[id] * index
  3. Set pwr to the maximum of (4 * num + den/2) / den and -8
  4. If PHY Revision < 3
    1. If index <= (31 - idle[id] +1)
      1. Set pwr to maximum of pwr and target[id] + 1
  5. Set regval[index] to pwr
2. Write N PHY table with ID (id + 26), length 64, offset 0, width 32, and data regval
Call N PHY TX Power Limit to Table
Call PHY TX Power Recalc Target
Write N PHY table with ID 26, length 84 offset 64, width 8 and data from adj_pwr_tbl_nphy
Write N PHY table with ID 27, length 84 offset 64, width 8 and data from adj_pwr_tbl_nphy
if phyhang_avoid is not zero
1. Call N PHY Stay In Carrier Search with argument 0 (disable)