Contents
Init Routine
- Accumulator 1 and 2 are both set to 0
Backup Radio Registers 0x43, 0x51, 0x52
Backup PHY Registers 0x15, 0x5A, 0x59, 0x58
- If this is a B PHY
Backup PHY Register offset 0x30
Backup Core Register 0x3EC
Write 0xFF to PHY Register 0x30
Write 0x3F3F to Core Register 0x3EC
If this is not a B PHY and (Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater)
Back up PHY Registers 0x811, 0x812, 0x814, 0x815, 0x429, 0x802
OR PHY Register 0x814 with 3
AND PHY Register 0x815 with 0xFFFC
AND PHY Register 0x429 with 0x7FFF
AND PHY Register 0x802 with 0xFFFC
If Loopback Gain is enabled
Backup PHY Register 0x80F
Backup PHY Register 0x810
- If the PHY Revision is 3 or greater
Write 0xC020 to PHY Register 0x80F
- Otherwise
Write 0x8020 to PHY Register 0x80F
Write 0 to PHY Register 0x810
Write the L = 0, P = 1, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write the PHY Register 0x811 value from the table below to PHY Register 0x811
OR Core Register 0x3E2 with 0x8000
Backup PHY Register 0x35
AND PHY Register 0x35 with 0xFF7F
Backup Core Register 0x3E6, 0x3F4
If the Analog Core Revision is 0
Write 0x122 to Core Register 0x3E6
- Otherwise
If the Analog Core Revision is 2 or greater
MaskSet PHY Register 0x3 with mask 0xFFBF and set with 0x40
OR Core Register 0x3F4 with 0x2000
Find the Radio Core Calibration value using the RCC Table
- If this is a B PHY
Write 0x26 into Radio Register 0x78
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 0, P = 1, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xBFAF to PHY Register 0x15
Write 0x1403 to PHY Register 0x2B
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 0, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xBFA0 to PHY Register 0x15
OR Radio Register 0x51 with 0x4
- If the Radio Revision is 8
Write 0x1F into Radio Register 0x43
- Otherwise
Write 0 to Radio Register 0x52
MaskSet Radio Register 0x43 with mask 0xFFF0 and set with 0x9
Write 0 to PHY Register 0x58
- Loop 16 times
Write 0x480 to PHY Register 0x5A
Write 0xC810 to PHY Register 0x59
Write 0xD to PHY Register 0x58
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xAFB0 to PHY Register 0x15
- Delay 10 uSec
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xEFB0 to PHY Register 0x15
- Delay 10 uSec
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 0 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xFFF0 to PHY Register 0x15
- Delay 20 uSec
Read the value of PHY Register 0x2D and add it to Accumulator 1
Write 0 to PHY Register 0x58
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xAFB0 to PHY Register 0x15
- Delay 10 uSec
Write 0 to PHY Register 0x58
- Add 1 to the value of Accumulator 1 then right shift by 9.
- Loop 16 times from 0 to 15
- Take the bit-reversed loop index (a 4 bit value) and left shift it by 1
- OR the result with 0x20
Write this value to Radio Register 0x78
Save the value of Radio Register 0x78
- Delay 10 usec
- Loop 16 times
Write 0xD80 to PHY Register 0x5A
Write 0xC810 to PHY Register 0x59
Write 0xD to PHY Register 0x58
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xAFB0 to PHY Register 0x15
- Delay 10 usec
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xEFB0 to PHY Register 0x15
- Delay 10 usec
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 0 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xFFF0 to PHY Register 0x15
- Delay 10 usec
Read the value of PHY Register 0x2D and add it to Accumulator 2
Write 0 to PHY Register 0x58
If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater
Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812
Write 0xAFB0 to PHY Register 0x15
- Increment Accumulator 2 then right shift by 8
- If Accumulator 1 is less than Accumulator 2, break from the loop
Restore the original value of PHY Register 0x15
Restore the original values of Radio Registers 0x51, 0x52, 0x43
Restore the original values of PHY Registers 0x5A, 0x59, 0x58
Restore the original value of Core Register 0x3E6
If the Analog Core Revision is not 0
Restore the original value of Core Register 0x3F4
Restore the original value of PHY Register 0x35
Perform the Synthetic PU Workaround (channel selection)
- If this is a B PHY
Restore the original value of PHY Register 0x30
Restore the original value of Core Register 0x3EC
If this isn't a B PHY and Core Flags has the G Mode Enable flag (0x20000000) set
AND Core Register 0x3E2 with 0x7FFF
Restore the value of PHY Registers 0x811, 0x812, 0x814, 0x815, 0x429 and 0x802
- If Loopback Gain is enabled
Restore PHY Registers 0x80F and 0x810
- If we went through all of the loops in Loop 2
Return the saved value of Radio Register 0x78
- Otherwise
Return the value from the RCC Table
Value Table
All values are 0 if Core Flags doesn't have the G Mode Enable flag (0x20000000) set and the PHY Revision isn't 2 or greater
Loopback Gain Disabled
PHY Revision < 7 or Board Flags BFL_EXTLNA isn't set
GPHY Register 0x811 Value |
0x1B3 |
GPHY Register 0x812 Value |
|||
L |
P |
D |
Value |
0 |
1 |
1 |
0x0FB2 |
0 |
0 |
1 |
0x00B2 |
1 |
0 |
1 |
0x30B2 |
1 |
0 |
0 |
0x30B3 |
Otherwise
GPHY Register 0x811 Value |
0x9B3 |
GPHY Register 0x812 Value |
|||
L |
P |
D |
Value |
0 |
1 |
1 |
0x8FB2 |
0 |
0 |
1 |
0x80B2 |
1 |
0 |
1 |
0x20B2 |
1 |
0 |
0 |
0x20B3 |
Otherwise
- If the Radio Revision is 8
- Take the Maximum Loopback Gain (in half dB) and add 0x3E to the value
- Otherwise
- Take the Maximum Loopback Gain (in half dB) and add 0x26 to the value
- Using the correct value from the table below, subtract it from the result
- Loop up to 16 times, from 0 to 15
- Subtract 6 times the loop position from the value found above
- If this result is less than 6
- Break the loop
- Use the final loop position value and the External LNA value below to find the table values
External LNA Control Table
Adjusted Maximum Loopback Gain Value |
External LNA Control Value |
Value to Subtract |
>= 0x46 |
0x3000 |
0x46 |
0x45 >= x >= 0x3A |
0x1000 |
0x3A |
0x39 >= x >= 0x2E |
0x2000 |
0x2E |
Otherwise |
0x0000 |
0x10 |
PHY Revision < 7 or Board Flags BFL_EXTLNA isn't set
GPHY Register 0x811 Value |
0x1B3 |
- OR the loop position value left shifted by 8 with the External LNA Control Value
OR this value with the table values below which are marked with Yes
GPHY Register 0x812 Value |
||||
L |
P |
D |
Value |
OR'd with the value above |
0 |
1 |
1 |
0x0F92 |
No |
0 |
0 |
1 |
0x0092 |
Yes |
1 |
0 |
1 |
0x0092 |
Yes |
1 |
0 |
0 |
0x0093 |
Yes |
Otherwise
GPHY Register 0x811 Value |
0x9B3 |
- If the value from the External LNA Control Value table isn't 0
- OR the the External LNA Control value with 0x8000
- OR the loop position value left shifted by 8 with the External LNA Control Value
OR this value with the table values below which are marked with Yes
GPHY Register 0x812 Value |
||||
L |
P |
D |
Value |
OR'd with the value above |
0 |
1 |
1 |
0x8F92 |
No |
0 |
0 |
1 |
0x8092 |
Yes |
1 |
0 |
1 |
0x2092 |
Yes |
1 |
0 |
0 |
0x2093 |
Yes |