Contents
Reading and Writing PHY Registers
PHY Registers are accessed by writing the PHY Register Address to Register 0x03FC, then reading or writing the 16 bit value through Register 0x03FE.
PHY register addresses consist of the following components:
Mask |
Meaning |
0x0C00 |
Routing value |
0x03FF |
Register offset |
Routing Value |
Meaning |
Notes |
0 |
Base PHY Registers |
A PHY - All Registers (including the OFDM ones) use this routing value |
G PHY - Common Registers and CCK Registers |
||
N PHY - All N PHY Registers use this routing value |
||
1 |
OFDM Registers |
G PHY Only |
2 |
Extended G PHY Registers |
G PHY Only |
3 |
B mode Registers |
N PHY Only |
Locking PHY registers against MAC use
On cores with revision < 3 the MAC needs to be suspended as parallel access to PHY registers from the MAC and host is not possible. On core revisions above that, the MAC needs to be forced to stay awake for host PHY register access by setting the device is awake MAC control bit. Note that for core revisions >= 5 the Microcode doesn't really ever test this bit so we don't know why it is set. Most likely forcing the MAC to stay awake is only required for core revisions 3 and 4.
Common Registers
These registers are used in all of the various layouts.
Offset |
Usage |
Notes |
0x00 |
used by microcode; used by host for OFDM part of G PHY |
OFDM (A) PHY Registers
For A PHYs, these registers are available using the Base Register routing bit. Many of these registers are also present in G PHYs and are made available by using the OFDM routing bit.
Offset |
Usage |
Notes |
0x01 |
G PHY only, is a regular register for others |
|
0x03 |
power down |
|
0x06 |
CRS Threshold 1 |
G PHY: rev > 1 |
0x10 |
RF override (control) |
radio related, used during radio on/off |
0x11 |
RF override (value) |
radio related, used during radio on/off |
0x12 |
GPIO out enable |
used on G PHYs only (during agc) |
0x13 |
TR lookup table (1) |
used on some A PHYs only |
0x14 |
TR lookup table (2) |
used on some A PHYs only |
0x15 |
digital gain (1) |
used on some G PHYs only |
0x16 |
digital gain (2) |
used on some G PHYs only |
0x17 |
digital gain (3) |
used on some G PHYs only |
0x18 |
desired power (?) |
|
0x19 |
PAR gain selection (?) |
|
0x1A |
min/max gain |
used on G PHYs only (during init) |
0x1B |
gain info |
|
0x1C |
A PHYs Only |
|
0x1D |
clip gain index |
used on some A PHYs only |
0x1F |
clip BO threshold |
related to gain control |
0x20 |
LPF Gain BO threshold |
(bits 7-4) |
0x22 |
CCK Gain BO threshold |
used on G PHYs only (during agc) |
0x24 |
clip power threshold |
used on some A PHYs only |
0x26 |
DC B0 |
used on G PHYs only (during agc) |
0x27 |
DC B1 |
related to antenna diversity |
0x29 |
CRS0 |
some control register |
0x2A |
related to gain control |
used on some A PHYs only |
0x2B |
antenna dwell register (bitfield) |
|
0x2C |
reset length |
more CRS control |
0x2D |
clip counter init |
TX Power (?) |
0x30 |
PLCP timeout STR0 minimum |
"Peak Count" (?); used on G PHYs only (during agc) |
0x33 |
|
used on some A PHYs only |
0x34 |
|
used on some A PHYs only (DC FC) |
0x35 |
scale factor (I) |
used on some A PHYs only (AFC DAC workaround) |
0x36 |
scale factor (Q) |
used on some A PHYs only (AFC DAC workaround) |
0x49 |
Viterbi offset |
Encore register, bit 0x200 indicates if encore is available |
0x55 |
LMS |
|
0x5A |
coarse estimation (?) |
APHY Status (?) |
0x5F |
PHY packet count (?) |
used by microcode as 0x45F on G PHY (but even on B PHY?) |
0x61 |
control |
|
0x63 |
RX comp coefficients |
A PHY only |
0x69 |
TX comp coefficients ("I/Q balance") |
used on A PHYs only (maybe G PHYs do this internally?) |
0x6A |
TX comp offset ("Minimum Baseband TX DC Bias") |
Used on A PHYs only |
0x6B |
Baseband TX DC Bias |
Used on A/N PHYs only |
0x6E |
rotate factor |
used on G PHYs only, only if PACTRL |
0x72 |
|
|
0x73 |
|
|
0x74 |
For Complex Tables Only |
|
0x75 |
RSSI filter B0 |
power control related, A PHY only |
0x76 |
RSSI filter B1 |
power control related, A PHY only |
0x77 |
RSSI filter B2 |
power control related, A PHY only |
0x78 |
RSSI filter A1 |
Hardware Power TSSI control; G PHYs |
0x79 |
RSSI filter A2 |
hardware power control related; G PHYs |
0x7A |
ADC Control |
|
0x7B |
TSSI status |
used by Microcode |
0x7C |
APHY Temperature Control |
(Sense?) |
0x7D |
APHY Temperature status |
RSSI related how? |
0x7F |
WRSSI/NRSSI |
|
0x81 |
N1/N2 gain settle |
used on G PHYs only (during agc) |
0x82 |
N1/P1 gain settle |
|
0x88 |
P1 computation time (?) |
used on G PHYs only (during agc) |
0x89 |
N1 computation time (?) |
used on G PHYs only (during agc) |
0x8A |
NRSSI threshold |
used on G PHYs only, used by Microcode for ACI |
0x8B |
antenna 2 dwell control |
used on G PHYs only (during agc) |
0x8C |
antenna WR settle register |
used on G PHYs only |
0x8D |
something related to antenna (?) |
used on G PHY rev 1 only (during agc) |
0x8E |
AUX clip threshold |
even used as 0x48E on A PHY in some place but that bit is most likely ignored |
0x93 |
clip powerdown threshold |
|
0x96 |
N1/P1/P2 ...? |
used on G PHYs only (during init) |
0xA0 |
clip N1/P1 index |
used on G PHYs only |
0xA1 |
clip P1/P2 index |
used on G PHYs only |
0xA2 |
clip N1/N2 index |
used on G PHYs only |
0xA3 |
clip threshold |
used on G PHYs only |
0xA4 |
CCK desired power |
used on G PHYs only (mistake somewhere? was "clip N1/P2 threshold") |
0xA5 |
CCK gain info |
used on G PHYs only, only 0x1A written for PHY rev 1 (CCK shift bits workaround) |
0xA7 |
CCK shiftbits GN reference |
used on G PHYs only (during init) |
0xA8 |
divider search index |
used on G PHYs only |
0xA9 |
clip P2 threshold |
used on G PHYs only |
0xAA |
clip P3 threshold |
used on G PHYs only |
0xAB |
divider search P1/P2 |
used on G PHYs only |
0xAC |
clip P1/P2 threshold |
used on G PHYs only |
0xAD |
divider search gain back |
used on G PHYs only |
0xAE |
divider search gain change |
used on G PHYs only |
0xB2 |
WW clip1 threshold |
used on some A PHYs only |
0xB5 |
WW clip0 index |
used on some A PHYs only |
0xB6 |
WW clip1 index |
used on some A PHYs only |
0xB7 |
WW clip2 index |
used on some A PHYs only |
0xB9 |
WW clip WRSSI index |
used on some A PHYs only |
0xBA |
WW clipvar threshold |
used on some A PHYs only |
0xBB |
|
used on some A PHYs only |
0xC0 |
CRS Threshold 1 |
G PHY only; rev == 1 |
0xC1 |
CRS Threshold 2 |
G PHY only; rev == 1 |
0xC4 |
Radar blank control |
A PHY Only |
0xC8 |
radar threshold (1) |
used by Microcode if radar workaround is enabled |
0xC9 |
EDON P1 |
used on G PHYs only (during agc) |
0xCC |
ρ² (rho not p) factor |
used on some A PHYs only |
0xDC |
RSSI selection lookup table 1 |
used on some A PHY rev 7/ana rev 4 only |
baseband config
mask |
contents |
0x8000 |
|
0x0180 |
antenna diversity selection |
antenna dwell
mask |
contents |
0x0100 |
automatic rx diversity start antenna (bit value = antenna) |
0x00FF |
|
antenna WR settle
mask |
contents |
0x2000 |
automatic rx diversity enabled |
Mask |
Usage |
0x1000 |
LNA Attenuation |
0x0E00 |
LNA Value |
0x01C0 |
HPF 1 |
0x0038 |
HPF 2 |
0x0007 |
HPF 3 |
CCK (B) PHY Registers
These registers are only present on G PHYs, they are available using the Base Register routing number
Offset |
Usage |
Notes |
`0x01 |
baseband config |
contains antenna 0/1 control bit; used by Microcode |
0x05 |
|
?? |
0x13 |
RX filter time up |
|
0x14 |
TX power override |
|
0x15 |
RF override |
previously called PGA Control, to be cleaned up |
0x18 |
frequency bandwidth control 1 |
|
0x1C |
|
|
0x20 |
RSSI threshold |
|
0x21 |
IQ threshold (high high) |
|
0x22 |
IQ threshold (high) |
|
0x23 |
IQ threshold (low) |
|
0x24 |
IQ threshold (low low) |
|
0x26 |
LNA gain range |
|
0x27 |
JSSI (PHY noise in lower 8 bits) |
used by Microcode |
0x28 |
TSSI control |
|
0x29 |
idle TSSI |
|
0x2A |
TR Loss Control |
|
0x2D |
LO leakage |
|
0x2E |
TX DC offset 1 |
BPHY Only (clean up: "Control Register Mask") |
0x2F |
TX DC offset 2 |
BPHY Only (clean up: "Control Register") |
0x30 |
Peak Count threshold |
|
0x32 |
diversity control |
|
0x33 |
Peak Energy (low) |
|
0x34 |
Peak Energy (high) |
|
0x35 |
Sync Control |
|
0x36 |
TX power control |
|
0x37 |
TX power estimation |
used by Microcode if hardware power control is enabled |
0x38 |
frequency bandwidth control 2 |
|
0x3E |
RF DC cancel control |
|
0x3F |
|
?? |
0x4E |
TX power base index |
power control related; used by microcode as well |
0x4F |
optional modes 2 |
hardware power control related? |
0x50 |
CCK LMS step |
|
0x5B |
LNA gain range 10 |
G only |
0x5C |
LNA gain range 32 |
G only |
0x5D |
optional modes |
|
0x5F |
PHY rx status (3) |
used by microcode as 0x45F on G PHY (but even on B PHY?) |
0x60 |
DAC control |
PHYs with Analog Core Type 1 have the baseband attenuation value here in bits 3-6, bits 2-5 otherwise |
0x61 |
|
?? |
0x78 |
RC calibration override |
?? |
0x79 ?? |
hardware power control related |
used by Microcode ?? |
0x88 - 0xA7 |
RSSI lookup table |
|
0xA8 - 0xC7 |
TSSI lookup table |
|
0x380 - 0x39F |
TSSI 2 power lookup table |
G PHY only (used for hardware power control) |
0x3A0 - 0x3BF |
LO comp lookup table ("DC lookup table") |
G PHY only (used for hardware power control) |
0x3C0 - 0x3FF |
TX gain lookup table |
G PHY only (used for hardware power control) |
Extended G PHY Registers
Or maybe these are the registers for the mysterious "analog"??
Offset |
Usage |
Notes |
0x01 |
G PHY control |
|
0x02 |
Classify Control |
0x1: cck, 0x2: ofdm, 0x100: ?? |
0x03 |
table number is in bits 0xFC00, table offset in bits 0x03FF |
|
0x04 |
Extended G PHY Table Data |
read or written after setting the control register |
0x0F |
DC offset 1 |
local oscillator control register mask (??) |
0x10 |
DC offset 2 |
local oscillator control register (??) |
0x11 |
RF Override |
|
0x12 |
|
|
0x14 |
Analog Override |
also used by Microcode if 4318 TSSI hostflag is set |
0x15 |
Analog override Value |
|
PGA Control
Mask |
Usage |
0x1000 |
LPF Flag |
0xEFA0 |
Unknown, always set |
0x0040 |
Low Bandwidth Flag |
These flags are OR'd with the PGA Value
RF Override Value
Mask |
Usage |
0xF000 |
LNA |
0x0F00 |
PGA |
0x0010 |
Unknown, always set |
0x0003 |
Bandwidth Flags |
Bandwidth Flags
Flag |
Usage |
0x0000 |
High Bandwidth |
0x0001 |
LPF |
0x0002 |
Low Bandwidth |
N PHY Registers
Offset |
Function |
Notes |
0x001 |
BB Config |
bit 0x4000: reset CCA; bit 0x8000: reset RX |
0x005 |
Channel |
|
0x007 |
TX Error |
|
0x009 |
Band Control |
bit 0x0001: current band |
0x00b |
Four-wire address |
Four-wire bus used for communication with Radio or other components? |
0x00c |
Four-wire data high |
|
0x00d |
Four-wire data low |
|
0x00e |
BIST (built-in self test) Status 0 |
|
0x00f |
BIST Status 1 |
|
0x018 |
Core 1 desired power |
|
0x019 |
Core 1 CCK desired power |
|
0x01a |
Core 1 barely clip backoff |
|
0x01b |
Core 1 CCK barely clip backoff |
|
0x01c |
Core 1 compute gain info |
bits 0x1f: gain backoff |
0x01d |
Core 1 CCK compute gain info |
0x1e0: CCK barely clip gain backoff value, 0x1f: gain backoff value |
0x01e |
Core 1 Min/Max gain |
Max: high byte, Min: low byte |
0x01f |
Core 1 CCK Min/Max gain |
Max: high byte, Min: low byte |
0x020 |
Core 1 initial gain code |
bit 0x0001: external LNA index |
0x021 |
Core 1 clip1 high gain code |
|
0x022 |
Core 1 clip1 medium gain code |
|
0x023 |
Core 1 clip1 low gain code |
|
0x024 |
Core 1 clip2 gain code |
|
0x025 |
Core 1 Filter gain |
|
0x026 |
Core 1 LPF Q HP F bandwidth |
|
0x027 |
Core 1 clip wideband threshold |
low 6 bits: clip 2, next 6 bits: clip 1 |
0x028 |
Core 1 W1 threshold |
|
0x029 |
Core 1 ED threshold |
|
0x02a |
Core 1 small sig threshold |
|
0x02b |
Core 1 NB clip threshold |
|
0x02c |
Core 1 clip1 threshold |
|
0x02d |
Core 1 clip2 threshold |
|
0x02e - 0x043 |
same as the ones above but for Core 2 instead of Core 1 |
|
0x044 |
CRS threshold 1 |
|
0x045 |
CRS threshold 2 |
|
0x046 |
CRS threshold 3 |
|
0x047 |
CRS control |
|
0x048 |
DC Filter address |
|
0x049 - 0x04b |
RX Filter 20 Numerator 0-2 |
|
0x04c - 0x04d |
RX Filter 20 Denominator 0-1 |
|
0x04e - 0x050 |
RX Filter 20 Numerator 10-12 |
|
0x051 - 0x052 |
RX Filter 20 Denominator 10-11 |
|
0x053 - 0x055 |
RX Filter 40 Numerator 0-2 |
|
0x056 - 0x057 |
RX Filter 40 Denominator 0-1 |
|
0x058 - 0x05a |
RX Filter 40 Numerator 10-12 |
|
0x05b - 0x05c |
RX Filter 40 Denominator 10-11 |
|
0x060 |
Packet processing reset length |
|
0x061 |
initial carrier detection length |
|
0x062 |
clip1 carrier detection length |
|
0x063 |
clip2 carrier detection length |
|
0x064 |
initial gain settle length |
|
0x065 |
clip1 gain settle length |
|
0x066 |
clip1 gain settle length |
|
0x067 |
packet gain settle length |
|
0x068 |
carrier search timeout length |
|
0x069 |
timing search timeout length |
|
0x06a |
energy drop timeout length |
|
0x06b |
clip1 NB dwell length |
|
0x06c |
clip2 NB dwell length |
|
0x06d |
W1 clip1 dwell length |
|
0x06e |
W1 clip2 dwell length |
|
0x06f |
W2 clip1 dwell length |
|
0x070 |
Payload carrier sense extension length |
|
0x071 |
energy drop carrier sense extension length |
|
0x072 |
Table address |
0xfc00: table ID, 0x3ff: table offset |
0x073 |
Table data (low) |
low 16 bits of table data, or for only 8 bits |
0x074 |
Table data (high) |
high 16 bits of table data, write high before low |
0x075 |
WWiSE length index |
|
0x076 |
TGNsync length index |
|
0x077 |
TX MAC IF Hold off |
|
0x078 |
RF control (command) |
bit 0x1: start sequence, bit 0x2: rx/tx, bits 0x38: core select, bit 0x40: POR force, 0x80: OE_POR force, 0x100: RX enable, 0x200: TX enable, 0x400: chip0 PU, 0xf000: seq en core |
0x07a |
RF control (RSSI others 1) |
0x1: RX PD, 0x2: TX PD, 0x4: PA PD, 0x30: RSSI control, 0xc0: LPF bandwidth, 0x100: HPF bandwidth high, 0x200: HIQ dis core |
0x07b |
RF control (RX gain 1) |
|
0x07c |
RF control (TX gain 1) |
|
0x07d |
RF control (RSSI others 2) |
(same as 1) |
0x07e |
RF control (RX gain 2) |
|
0x07f |
RF control (TX gain 2) |
|
0x080 |
RF control (RSSI others 3) |
|
0x081 |
RF control (RX gain 3) |
|
0x082 |
RF control (TX gain 3) |
|
0x083 |
RF control (RSSI others 4) |
|
0x084 |
RF control (RX gain 4) |
|
0x085 |
RF control (TX gain 4) |
|
0x087 |
Core 1 TX I/Q comp offset |
|
0x088 |
Core 2 TX I/Q comp offset |
|
0x08b |
Core 1 TX control |
|
0x08c |
Core 2 TX control |
|
0x08f |
AFE (analog front-end?) control override1 |
TBD |
0x090 |
scram signal control |
0x7f: initial state value, 0x80: scram control mode, 0x100: scram index control enable, 0xfe00: scram start bit |
0x091 |
RF control (intc 1) |
|
0x092 |
RF control (intc 2) |
|
0x093 |
RF control (intc 3) |
|
0x094 |
RF control (intc 4) |
|
0x095 |
# datatones WWiSE |
|
0x096 |
# datatones TGNsync |
|
0x097 |
signal field mod WWiSE |
|
0x098 |
legacy signal field mod 11n |
|
0x099 |
HT signal field mod 11n |
|
0x09a |
Core 1 RX I/Q comp A0 |
|
0x09b |
Core 1 RX I/Q comp B0 |
|
0x09c |
Core 2 RX I/Q comp A1 |
|
0x09d |
Core 2 RX I/Q comp B1 |
|
0x0a0 |
RX Control |
bit 0x0010: band select upper 20 |
0x0a1 |
RF seq mode |
0x1: core active override, 0x2: trigger override |
0x0a2 |
RF seq core active |
0xf: enable TX, 0xf0: enable RX, 0xf00: disable tx, 0xf000: disable RX; common values: chain 0: 0x11, chain 1: 0x22 |
0x0a3 |
RF seq trigger |
0x1: RX2TX, 0x2: TX2RX, 0x4: update gain H, 0x8: update gain L, 0x10: update gain U, 0x20: reset to RX |
0x0a4 |
RF seq status |
same as trigger |
0x0a5 |
AFE (analog front-end?) control override |
TBD |
0x0a6 |
AFE control core 1 |
TBD |
0x0a7 |
AFE control core 2 |
same as 1 |
0x0a8 |
AFE control core 3 |
same as 1? |
0x0a9 |
AFE control core 4 |
same as 1? |
0x0aa |
AFE control DAC gain 1 |
|
0x0ab |
AFE control DAC gain 2 |
|
0x0ac |
AFE control DAC gain 3 |
|
0x0ad |
AFE control DAC gain 4 |
|
0x0ae |
STR Address 1 |
|
0x0af |
STR Address 2 |
|
0x0b0 |
Classifier Control |
bit 0x0001: CCK enable |
0x0b1 |
I/Q flip |
0x1: adc1, 0x10: adc2 |
0x0b2 |
SISO SNR threshold |
|
0x0b3 |
sigma N multiplier |
|
0x0b4 |
TX MAC delay |
|
0x0b5 |
TX frame delay |
|
0x0b6 |
ML parameters |
|
0x0b7 |
ML control |
|
0x0b8 |
WWiSE 20 N cyc data |
|
0x0b9 |
WWiSE 40 N cyc data |
|
0x0ba |
TGNsync 20 N cyc data |
|
0x0bb |
TGNsync 40 N cyc data |
|
0x0bc |
initial swizzle pattern |
|
0x0bd |
TX tail count value |
|
0x0be |
B PHY control 1 |
|
0x0bf |
B PHY control 2 |
0x1f: LUT index, 0x7fe0: MAC delay |
0x0c0 |
I/Q LO cal command |
0x8000: I/Q LO cal enable |
0x0c1 |
I/Q LO cal command N num |
|
0x0c2 |
I/Q LO cal command G control |
|
0x0c3 |
sample command |
0x2: stop |
0x0c4 |
sample loop count |
|
0x0c5 |
sample wait count |
|
0x0c6 |
sample depth count |
|
0x0c7 |
sample status |
|
0x0c8 |
GPIO low out enable |
|
0x0c9 |
GPIO high out enable |
|
0x0ca |
GPIO select |
|
0x0cb |
GPIO clock control |
|
0x0cc |
TX filter 20 coeff A stage 0 |
|
0x0cd |
TX filter 20 coeff A stage 1 |
|
0x0ce |
TX filter 20 coeff A stage 2 |
|
0x0cf |
TX filter 20 coeff B32 stage 0 |
|
0x0d0 |
TX filter 20 coeff B1 stage 0 |
|
0x0d1 |
TX filter 20 coeff B32 stage 1 |
|
0x0d2 |
TX filter 20 coeff B1 stage 1 |
|
0x0d3 |
TX filter 20 coeff B32 stage 2 |
|
0x0d4 |
TX filter 20 coeff B1 stage 2 |
|
0x0d5 |
signal fld tolerance |
|
0x0d6 |
TX service field |
|
0x0d7 |
AFE seq RX2TX power up/down delay |
|
0x0d8 |
AFE seq TX2RX power up/down delay |
|
0x0d9 |
TGNsync scram init 0 |
|
0x0da |
TGNsync scram init 1 |
|
0x0db |
initial swizzle pattern leg (legacy?) |
|
0x0dc |
B PHY control 3 |
0xff: scale, 0xff00: frame start count value |
0x0dd |
B PHY control 4 |
|
0x0de |
Core 1 TX BB multiplier (?) |
|
0x0df |
Core 2 TX BB multiplier (?) |
|
0x0e1 |
TX filter 40 coeff A stage 0 |
|
0x0e2 |
TX filter 40 coeff A stage 1 |
|
0x0e3 |
TX filter 40 coeff A stage 2 |
|
0x0e4 |
TX filter 40 coeff B32 stage 0 |
|
0x0e5 |
TX filter 40 coeff B1 stage 0 |
|
0x0e6 |
TX filter 40 coeff B32 stage 1 |
|
0x0e7 |
TX filter 40 coeff B1 stage 1 |
|
0x0e8 |
TX filter 40 coeff B32 stage 2 |
|
0x0e9 |
TX filter 40 coeff B1 stage 2 |
|
0x0ea |
BIST status 2 |
|
0x0eb |
BIST status 3 |
|
0x0ec |
RF control override |
TBD |
0x0ed |
MIMO Config |
0x4: greenfield or mixed mode, 0x100: greenfield/mixed mode auto |
0x0ee |
Radar blank control |
|
0x0ef |
antenna 0 radar FIFO control |
|
0x0f0 |
antenna 1 radar FIFO control |
|
0x0f1 |
antenna 0 radar FIFO data |
|
0x0f2 |
antenna 1 radar FIFO data |
|
0x0f3 |
radar threshold 0 |
|
0x0f4 |
radar threshold 1 |
|
0x0f5 |
radar threshold 0R |
|
0x0f6 |
radar threshold 1R |
|
0x0f7 |
carrier sense 20 in 40 dwell length |
|
0x0f8 |
RF control LUT TRSW lower 1 |
|
0x0f9 |
RF control LUT TRSW upper 1 |
|
0x0fa |
RF control LUT TRSW lower 2 |
|
0x0fb |
RF control LUT TRSW upper 2 |
|
0x0fc |
RF control LUT TRSW lower 3 |
|
0x0fd |
RF control LUT TRSW upper 3 |
|
0x0fe |
RF control LUT TRSW lower 4 |
|
0x0ff |
RF control LUT TRSW upper 4 |
|
0x100 |
RF control LUT LNA PA 1 |
|
0x101 |
RF control LUT LNA PA 2 |
|
0x102 |
RF control LUT LNA PA 3 |
|
0x103 |
RF control LUT LNA PA 4 |
|
0x104 |
TGNsync CRC mask 0 |
|
0x105 |
TGNsync CRC mask 1 |
|
0x106 |
TGNsync CRC mask 2 |
|
0x107 |
TGNsync CRC mask 3 |
|
0x108 |
TGNsync CRC mask 4 |
|
0x109 |
CRC polynomial |
|
0x10a |
# sig count |
|
0x10b |
sig start bit control |
|
0x10c |
CRC polynomial order |
|
0x10d |
RF control core swap table 0 |
|
0x10e |
RF control core swap table 1 |
|
0x10f |
RF control core swap table 2+others |
|
0x111 |
B PHY control 5 |
|
0x112 |
RF seq LPF bandwidth |
|
0x114 |
TSSI bias val 1 |
0xff: bias, 0xff00: value |
0x115 |
TSSI bias val 2 |
like 1 |
0x118 |
estimated power 1 |
0xff: estimated power, 0x100: estimated power valid |
0x119 |
estimated power 2 |
like 1 |
0x11c |
TSSI max TX frame delay time |
0xff: max TX frame delay time |
0x11d |
TSSI max TSSI delay time |
0xff: max TSSI delay time |
0x11e |
TSSI idle 1 |
0xff: idle TSSI |
0x11f |
TSSI idle 2 |
0xff: idle TSSI |
0x122 |
TSSI mode |
0x1: TSSI enable, 0x2: power det enable |
0x123 |
RX Macif mode |
|
0x124 |
CRS idle time CRS-on count (low) |
|
0x125 |
CRS idle time CRS-on count (high) |
|
0x126 |
CRS idle time measure time count (low) |
|
0x127 |
CRS idle time measure time count (high) |
|
0x128 |
sample tail wait count |
|
0x129 |
I/Q estimate command |
0x1: start, 0x2: mode |
0x12a |
I/Q estimate wait time |
0xff: wait time |
0x12b |
I/Q estimate sample count |
|
0x12c |
I/Q estimate I/Q acc lo 0 |
|
0x12d |
I/Q estimate I/Q acc hi 0 |
|
0x12e |
I/Q estimate I power acc lo 0 |
|
0x12f |
I/Q estimate I power acc hi 0 |
|
0x130 |
I/Q estimate Q power acc lo 0 |
|
0x131 |
I/Q estimate Q power acc hi 0 |
|
0x134 |
I/Q estimate I/Q acc lo 1 |
|
0x135 |
I/Q estimate I/Q acc hi 1 |
|
0x136 |
I/Q estimate I power acc lo 1 |
|
0x137 |
I/Q estimate I power acc hi 1 |
|
0x138 |
I/Q estimate Q power acc lo 1 |
|
0x139 |
I/Q estimate Q power acc hi 1 |
|
0x13a |
MIMO PHY CRS TX extension |
|
0x13b |
power det 1 |
|
0x13c |
power det 2 |
|
0x13f |
RSSI max RSSI delay time |
|
0x141 |
pilot data weight 0 |
(same as 1?) |
0x142 |
pilot data weight 1 |
0xf000: 64-qam, 0x0f00: 16-qam, 0x00f0: qpsk, 0x000f: bpsk |
0x143 |
pilot data weight 2 |
(same as 1?) |
0x144 |
FM demodulation config |
|
0x145 |
Phase track alpha 0 |
|
0x146 |
Phase track alpha 1 |
|
0x147 |
Phase track alpha 2 |
|
0x148 |
Phase track beta 0 |
|
0x149 |
Phase track beta 1 |
|
0x14a |
Phase track beta 2 |
|
0x14b |
Phase track change 0 |
|
0x14c |
Phase track change 1 |
|
0x14d |
Phase track offset |
|
0x14e |
RF control debug |
|
0x150 |
CCK shiftbits reference var |
|
0x152 |
override digital gain 0 |
(same as 1?) |
0x153 |
override digital gain 1 |
0x7: force digital gain value, 0x8: force digital gain enable, 0xff00: cck digital gain enable count value |
0x156 |
BIST status 4 |
|
0x157 |
Radar MA length |
|
0x158 |
Radar search control |
|
0x159 |
VLD data tones sig |
|
0x15a |
VLD data tones data |
|
0x15b |
Core 1 B PHY RX I/Q comp A0 |
|
0x15c |
Core 1 B PHY RX I/Q comp B0 |
|
0x15d |
Core 2 B PHY RX I/Q comp A1 |
|
0x15e |
Core 2 B PHY RX I/Q comp B1 |
|
0x160 |
frequency gain 0 |
|
0x161 |
frequency gain 1 |
|
0x162 |
frequency gain 2 |
|
0x163 |
frequency gain 3 |
|
0x164 |
frequency gain 4 |
|
0x165 |
frequency gain 5 |
|
0x166 |
frequency gain 6 |
|
0x167 |
frequency gain 7 |
|
0x168 |
frequency gain bypass |
|
0x169 |
TR loss value |
|
0x16a |
Core 1 ADC clip |
|
0x16b |
Core 2 ADC clip |
|
0x16f |
LTRN offset gain |
|
0x170 |
LTRN offset |
|
0x171 |
# data tones WWiSE 20 sig |
|
0x172 |
# data tones WWiSE 40 sig |
|
0x173 |
# data tones TGNsync 20 sig |
|
0x174 |
# data tones TGNsync 40 sig |
|
0x175 |
WWiSE CRC mask 0 |
|
0x176 |
WWiSE CRC mask 1 |
|
0x177 |
WWiSE CRC mask 2 |
|
0x178 |
WWiSE CRC mask 3 |
|
0x179 |
WWiSE CRC mask 4 |
|
0x17a |
channel estimate CDD shift |
|
0x17b |
HT AGC wait counters |
|
0x17c |
SQ params |
|
0x17d |
MCS dup 6M |
|
0x17e |
# data tones dup 40 |
|
0x17f |
dup40 TGNsync cycle data |
|
0x180 |
dup40 GF format BL address |
|
0x181 |
dup40 format BL addr |
|
0x182 |
legacy dup frm table addr |
|
0x183 |
packet processing debug |
|
0x184 |
pilot cycle counter 1 |
|
0x185 |
pilot cycle counter 2 |
|
0x186 |
TX filter 20 coeff stage 0 A1 |
|
0x187 |
TX filter 20 coeff stage 0 A2 |
|
0x188 |
TX filter 20 coeff stage 1 A1 |
|
0x189 |
TX filter 20 coeff stage 1 A2 |
|
0x18a |
TX filter 20 coeff stage 2 A1 |
|
0x18b |
TX filter 20 coeff stage 2 A2 |
|
0x18c |
TX filter 20 coeff stage 0 B1 |
|
0x18d |
TX filter 20 coeff stage 0 B2 |
|
0x18e |
TX filter 20 coeff stage 0 B3 |
|
0x18f |
TX filter 20 coeff stage 1 B1 |
|
0x190 |
TX filter 20 coeff stage 1 B2 |
|
0x191 |
TX filter 20 coeff stage 1 B3 |
|
0x192 |
TX filter 20 coeff stage 2 B1 |
|
0x193 |
TX filter 20 coeff stage 2 B2 |
|
0x194 |
TX filter 20 coeff stage 2 B3 |
|
0x195 |
TX filter 40 coeff stage 0 A1 |
|
0x196 |
TX filter 40 coeff stage 0 A2 |
|
0x197 |
TX filter 40 coeff stage 1 A1 |
|
0x198 |
TX filter 40 coeff stage 1 A2 |
|
0x199 |
TX filter 40 coeff stage 2 A1 |
|
0x19a |
TX filter 40 coeff stage 2 A2 |
|
0x19b |
TX filter 40 coeff stage 0 B1 |
|
0x19c |
TX filter 40 coeff stage 0 B2 |
|
0x19d |
TX filter 40 coeff stage 0 B3 |
|
0x19e |
TX filter 40 coeff stage 1 B1 |
|
0x19f |
TX filter 40 coeff stage 1 B2 |
|
0x1a0 |
TX filter 40 coeff stage 1 B3 |
|
0x1a1 |
TX filter 40 coeff stage 2 B1 |
|
0x1a2 |
TX filter 40 coeff stage 2 B2 |
|
0x1a3 |
TX filter 40 coeff stage 2 B3 |
|
0x1a4 |
RSSI multiplication coefficient 0 I RSSI X |
|
0x1a5 |
RSSI multiplication coefficient 0 I RSSI Y |
|
0x1a6 |
RSSI multiplication coefficient 0 I RSSI Z |
|
0x1a7 |
RSSI multiplication coefficient 0 I TBD |
|
0x1a8 |
RSSI multiplication coefficient 0 I power det |
|
0x1a9 |
RSSI multiplication coefficient 0 I TSSI |
|
0x1aa |
RSSI multiplication coefficient 0 Q RSSI X |
|
0x1ab |
RSSI multiplication coefficient 0 Q RSSI Y |
|
0x1ac |
RSSI multiplication coefficient 0 Q RSSI Z |
|
0x1ad |
RSSI multiplication coefficient 0 Q TBD |
|
0x1ae |
RSSI multiplication coefficient 0 Q power det |
|
0x1af |
RSSI multiplication coefficient 0 Q TSSI |
|
0x1b0 |
RSSI multiplication coefficient 1 I RSSI X |
|
0x1b1 |
RSSI multiplication coefficient 1 I RSSI Y |
|
0x1b2 |
RSSI multiplication coefficient 1 I RSSI Z |
|
0x1b3 |
RSSI multiplication coefficient 1 I TBD |
|
0x1b4 |
RSSI multiplication coefficient 1 I power det |
|
0x1b5 |
RSSI multiplication coefficient 1 I TSSI |
|
0x1b6 |
RSSI multiplication coefficient 1 Q RSSI X |
|
0x1b7 |
RSSI multiplication coefficient 1 Q RSSI Y |
|
0x1b8 |
RSSI multiplication coefficient 1 Q RSSI Z |
|
0x1b9 |
RSSI multiplication coefficient 1 Q TBD |
|
0x1ba |
RSSI multiplication coefficient 1 Q power det |
|
0x1bb |
RSSI multiplication coefficient 1 Q TSSI |
|
0x1bc |
sample collect wait counter |
|
0x1bd |
pass-through counter |
|
0x1c4 |
LTRN offset gain 20L |
|
0x1c5 |
LTRN offset 20L |
|
0x1c6 |
LTRN offset gain 20U |
|
0x1c7 |
LTRN offset 20U |
|
0x1c8 |
DSSS/CCK gain settle length |
|
0x1c9 |
GPIO low out |
|
0x1ca |
GPIO high out |
|
0x1cb |
CRS check |
|
0x1cc |
ML/logss ratio |
|
0x1cd |
dup scale |
|
0x1ce |
BW 1a |
|
0x1cf |
BW 2 |
|
0x1d0 |
BW 3 |
|
0x1d1 |
BW 4 |
|
0x1d2 |
BW 5 |
|
0x1d3 |
BW 6 |
|
0x1d4 |
Coarse length 0 |
|
0x1d5 |
Coarse length 1 |
|
0x1d6 |
CRS threshold 1 U |
|
0x1d7 |
CRS threshold 2 U |
|
0x1d8 |
CRS threshold 3 U |
|
0x1d9 |
CRS control U |
|
0x1da |
CRS threshold 1 L |
|
0x1db |
CRS threshold 2 L |
|
0x1dc |
CRS threshold 3 L |
|
0x1dd |
CRS control L |
|
0x1de |
STR address 1 U |
|
0x1df |
STR address 2 U |
|
0x1e0 |
STR address 1 L |
|
0x1e1 |
STR address 2 L |
|
0x1e2 |
CRS check 1 |
|
0x1e3 |
CRS check 2 |
|
0x1e4 |
CRS check 3 |
|
0x1e5 |
Jump step 0 |
|
0x1e6 |
Jump step 1 |
|
0x1e7 |
TX power control command |
0x7f: init (common value: 0x40), 0x2000: power control coefficients, 0x4000: HW TX power control enable, 0x8000: TX power control enable |
0x1e8 |
TX power control N num |
0xff: N TSSI delay, 0x700: N PT integer log2 |
0x1e9 |
TX power control idle TSSI |
0x3f: idle tssi0, 0x3f00: idle tssi1, 0x8000: raw TSSI offset bin format |
0x1ea |
TX power control target power |
0xff: power 0, 0xff00: power 1 |
0x1eb |
TX power control base index |
0x7f: uC base index 0, 0x7f00: uC base index 1, 0x8000: load base index |
0x1ec |
TX power control power index |
0x7f: uC power index 0, 0x7f00: uC base index 1, 0x8000: load power index |
0x1ed |
Core 1 TX power control status |
0xff: estimated power, 0x7f00: base index, 0x8000: estimated power valid |
0x1ee |
Core 2 TX power control status |
same as core 1 |
0x1ef |
small sig gain settle length |
|
0x1f0 |
PHY stats gain info 0 |
|
0x1f1 |
PHY stats gain info 1 |
|
0x1f2 |
PHY stats frequency estimate |
|
0x1f3 |
PHY stats ADV retard |
|
0x1f4 |
PHY loopback mode |
|
0x1f5 |
tone map index 20/1 |
|
0x1f6 |
tone map index 20/2 |
|
0x1f7 |
tone map index 20/3 |
|
0x1f8 |
tone map index 40/1 |
|
0x1f9 |
tone map index 40/2 |
|
0x1fa |
tone map index 40/3 |
|
0x1fb |
tone map index 40/4 |
|
0x1fc |
pilot tone map index 1 |
|
0x1fd |
pilot tone map index 2 |
|
0x1fe |
pilot tone map index 3 |
|
0x1ff |
TX RIFS frame delay |
|
0x200 |
AFE seq rx2tx power up/down delay 40M |
|
0x201 |
AFE seq tx2rx power up/down delay 40M |
|
0x202 |
AFE seq rx2tx power up/down delay 20M |
|
0x203 |
AFE seq tx2rx power up/down delay 20M |
|
0x204 |
RX signal control |
|
0x205 |
RX pilot cycle counter 0 |
|
0x206 |
RX pilot cycle counter 1 |
|
0x207 |
RX pilot cycle counter 2 |
|
0x208 |
AFE seq rx2tx power up/down delay 10M |
|
0x209 |
AFE seq tx2rx power up/down delay 10M |
|
0x20a |
DSSS/CCK CRS extension length |
|
0x20b |
ML/logss ratio slope |
|
0x20c |
RIFS search timeout length |
|
0x20d |
TX real frame delay |
|
0x20e |
high power antenna switch treshold |
|
0x210 |
ED CRS assert threshold 0 |
|
0x211 |
ED CRS assert threshold 1 |
|
0x212 |
ED CRS deassert threshold 0 |
|
0x213 |
ED CRS deassert threshold 1 |
|
0x214 |
STR wait time 20U |
|
0x215 |
STR wait time 20L |
|
0x216 |
Tone map index 657M |
|
0x217 |
HT signal tones |
|
0x219 |
RSSI value 1 |
|
0x21a |
RSSI value 2 |
|
0x21d |
channel estimate hang |
|
0x221 |
fine RX 2 clock gate control |
0x8: decode gated clocks |
0x222 |
TX power control init |
0xff: power index init 1 |
0x297 |
PAPD Enable0 |
TBD |
0x298 |
EPS Table Adj0 |
TBD |
0x29b |
PAPD Enable1 |
TBD |
0x29c |
EPS Table Adj1 |
TBD |
0x29d |
EPS OverrideI1 |
|
0x29e |
EPS Overrideq1 |
|
0x29f |
PAPD Cal Address |
|
0x2a0 |
PAPD Cal Yref |
|
0x2a1 |
PAPD Cal Settle |
|
0x2a2 |
PAPD Cal Correlate |
|
0x2a3 |
PAPD Cal Shift0 |
|
0x2a4 |
PAPD Cal Shift1 |
|
LP PHY
common
Offset |
Meaning |
Notes |
0x000 |
B PHY version |
|
0x001 |
B PHY BBConfig |
|
0x004 |
B PHY RX Status0 |
|
0x005 |
B PHY RX Status1 |
|
0x006 |
B PHY CRS Thresh |
|
0x007 |
B PHY TxError |
|
0x008 |
B PHY Channel |
|
0x009 |
B PHY workaround |
|
0x00a |
B PHY Test |
|
0x00b |
B PHY Fourwire Address |
|
0x00c |
B PHY Fourwire Data Hi |
|
0x00d |
B PHY Fourwire Data Lo |
|
0x00e |
B PHY Bist Status |
|
0x010 |
PA Ramp TX Timeout |
|
0x011 |
RF Synth DC Timer |
|
0x012 |
PA ramp TX Time in |
|
0x013 |
RX Filter Time in |
|
0x018 |
PLL Coefficient(s) |
|
0x019 |
PLL Out |
|
0x020 |
RSSI Threshold |
|
0x021 |
IQ Threshold HH |
|
0x022 |
IQ Threshold H |
|
0x023 |
IQ Threshold L |
|
0x024 |
IQ Threshold LL |
|
0x025 |
AGC Gain |
|
0x026 |
LNA Gain Range |
|
0x027 |
JSSI |
|
0x028 |
TSSI Control |
|
0x029 |
TSSI |
|
0x02a |
TR Loss |
|
0x02b |
LO Leakage |
|
0x02c |
LO RSSIAcc |
|
0x02d |
LO IQ Mag Acc |
|
0x02e |
TX DCOffset1 |
|
0x02f |
TX DCOffset2 |
|
0x030 |
|
|
0x031 |
|
|
0x032 |
|
|
0x033 |
PeakEnergyL |
|
0x034 |
PeakEnergyH |
|
0x035 |
|
|
0x038 |
|
|
0x039 |
|
|
0x03d |
|
|
0x040 |
SfdDetectBlockTIme |
|
0x041 |
SFDTimeOut |
|
0x042 |
SFDControl |
|
0x043 |
rxDebug |
|
0x044 |
RX DelayComp |
|
0x045 |
CRSDropoutTimeout |
|
0x046 |
|
|
0x047 |
PR3931 |
|
0x048 |
DSSSCoeff1 |
|
0x049 |
DSSSCoeff2 |
|
0x04a |
CCKCoeff1 |
|
0x04b |
CCKCoeff2 |
|
0x04c |
TRCorr |
|
0x04d |
|
|
0x04f |
|
|
0x050 |
CCKLMSStepSize |
|
0x051 |
DFEBypass |
|
0x052 |
CCKStartDelayLong |
|
0x053 |
CCKStartDelayShort |
|
0x054 |
|
|
0x055 |
PProcOnOff |
|
0x05b |
LNAGainTwoBit10 |
|
0x05c |
LNAGainTwoBit32 |
|
0x05d |
|
|
0x05e |
B PHY RX Status2 |
|
0x05f |
B PHY RX Status3 |
|
0x063 |
pwdnDacDelay |
|
0x067 |
FineDigiGain Control |
|
0x068 |
Lg2GainTblLNA8 |
|
0x069 |
Lg2GainTblLNA28 |
|
0x06a |
GainTblLNATrSw |
|
0x06b |
|
|
0x06c |
lg2InitGain |
|
0x06d |
|
|
0x06e |
LNAGainTwoBit54 |
|
0x06f |
LNAGainTwoBit76 |
|
0x070 |
JSSIControl |
|
0x071 |
Lg2GainTblLNA44 |
|
0x072 |
Lg2GainTblLNA62 |
|
0x400 |
Version |
|
0x401 |
BBConfig |
|
0x404 |
RX Status0 |
|
0x405 |
RX Status1 |
|
0x407 |
TX Error |
|
0x408 |
Channel |
|
0x409 |
workAround |
|
0x40b |
Fourwire Address |
|
0x40c |
|
|
0x40d |
|
|
0x40e |
|
|
0x40f |
|
|
0x410 |
crsgain Control |
|
0x411 |
ofdmPower Thresh0 |
|
0x412 |
ofdmPower Thresh1 |
|
0x413 |
ofdmPower Thresh2 |
|
0x414 |
dsssPower Thresh0 |
|
0x415 |
dsssPower Thresh1 |
|
0x416 |
MinPower Level |
|
0x417 |
ofdmSyncThresh0 |
|
0x418 |
ofdmSyncThresh1 |
|
0x419 |
|
|
0x41a |
IDLEafterPktRXTimeout |
|
0x41b |
LTRN Control |
|
0x41c |
DCOffsetTransient |
|
0x41d |
|
|
0x41e |
|
|
0x41f |
|
|
0x420 |
|
|
0x421 |
ofdmSyncTimer Control |
|
0x422 |
WaitforPHYSelTimeout |
|
0x423 |
HiGainDB |
|
0x424 |
LowGainDB |
|
0x425 |
VeryLowGainDB |
|
0x426 |
gainMismatch |
|
0x427 |
gaindirectMismatch |
|
0x428 |
Power Thresh0 |
|
0x429 |
Power Thresh1 |
|
0x42a |
Detector Delay Adjust |
|
0x42b |
Reduced Detector Delay |
|
0x42c |
data Timeout |
|
0x42d |
correlator Dis Delay |
|
0x42e |
Diversity GainBack |
|
0x42f |
DSSS Confirm Cnt |
|
0x430 |
DC Blank Interval |
|
0x431 |
gain Mismatch Limit |
|
0x432 |
crs ed thresh |
|
0x433 |
phase shift Control |
|
0x434 |
Input PowerDB |
|
0x435 |
ofdm sync Control |
|
0x436 |
Afe ADC Control 0 |
|
0x437 |
Afe ADC Control 1 |
|
0x438 |
Afe ADC Control 2 |
|
0x439 |
Afe DAC Control |
|
0x43a |
Afe Control |
|
0x43b |
Afe Control Ovr |
|
0x43c |
Afe Control OvrVal |
|
0x43d |
Afe RSSI Control 0 |
|
0x43e |
Afe RSSI Control 1 |
|
0x43f |
Afe RSSI Sel |
|
0x440 |
Radar Thresh |
|
0x441 |
Radar blank Interval |
|
0x442 |
Radar min fm Interval |
|
0x443 |
Radar gain timeout |
|
0x444 |
Radar pulse timeout |
|
0x445 |
Radar detect FM Control |
|
0x446 |
Radar detect En |
|
0x447 |
Radar Rd Data Reg |
|
0x448 |
LP PHY Control |
Only for PHY revision < 2 (?) |
0x449 |
classifier Control |
|
0x44a |
reset Control |
|
0x44b |
ClkEn Control |
|
0x44c |
RF Override 0 |
|
0x44d |
RF Override Val 0 |
|
0x44e |
TR Lookup 1 |
|
0x44f |
TR Lookup 2 |
|
0x450 |
|
|
0x451 |
iqlo Cal Cmd |
|
0x452 |
iqlo Cal Cmd N num |
|
0x453 |
iqlo Cal Cmd G control |
|
0x454 |
macint Debug Register |
|
0x455 |
Table Address |
|
0x456 |
|
|
0x457 |
|
|
0x458 |
phy CRS Enable Address |
|
0x459 |
Idletime Control |
|
0x45a |
Idletime CRS On Lo |
|
0x45b |
Idletime CRS On Hi |
|
0x45c |
Idletime Meas Time Lo |
|
0x45d |
Idletime Meas Time Hi |
|
0x45e |
Reset len Ofdm TX Address |
|
0x45f |
Reset len Ofdm RX Address |
|
0x460 |
reg crs enable |
|
0x461 |
PLCP Tmt Str0 Ctr Min |
|
0x462 |
Pkt fsm Reset Len Value |
|
0x463 |
readsym2reset Control |
|
0x464 |
Dc filter delay1 |
|
0x465 |
packet rx Active timeout |
|
0x466 |
ed timeoutValue |
|
0x467 |
hold CRS On Value |
|
0x469 |
ofdm tx phy CRS Delay Value |
|
0x46a |
cck tx phy CRS Delay Value |
|
0x46b |
Ed on confirm Timer Value |
|
0x46c |
Ed offset confirm Timer Value |
|
0x46d |
phy CRS offset Timer Value |
|
0x470 |
ADC Compensation Control |
|
0x471 |
log2 RBPSK Address |
|
0x472 |
log2 RQPSK Address |
|
0x473 |
log2 R16QAM Address |
|
0x474 |
log2 R64QAM Address |
|
0x475 |
offset BPSK Address |
|
0x476 |
offset QPSK Address |
|
0x477 |
offset 16QAM Address |
|
0x478 |
offset 64QAM Address |
|
0x479 |
Alpha1 |
|
0x47a |
Alpha2 |
|
0x47b |
Beta1 |
|
0x47c |
Beta2 |
|
0x47d |
Loop Num Address |
|
0x47e |
Str Collmax Sample Address |
|
0x47f |
Max Sample Coarse/Fine Address |
|
0x480 |
Max Sample Coarse/Str0Ctr Address |
|
0x481 |
IQ Enable Wait Time Address |
|
0x482 |
IQ Num Samples Address |
|
0x483 |
IQ Acc Hi Address |
|
0x484 |
IQ Acc Lo Address |
|
0x485 |
IQ I PWR Acc Hi Address |
|
0x486 |
IQ I PWR Acc Lo Address |
|
0x487 |
IQ Q PWR Acc Hi Address |
|
0x488 |
IQ Q PWR Acc Lo Address |
|
0x489 |
|
|
0x48a |
RotorPhase Address |
|
0x48b |
AdvancedRetardRotor Address |
|
0x48d |
rssiAdcdelay Control Address |
|
0x48e |
tssiStatus Address |
|
0x48f |
tempsenseStatus Address |
|
0x490 |
tempsense Control Address |
|
0x491 |
wrssistatus Address |
|
0x492 |
mufactoraddr |
|
0x493 |
scramstate Address |
|
0x494 |
txholdoffaddr |
|
0x495 |
pktgainval Address |
|
0x496 |
Coarseestim Address |
|
0x497 |
state Transition Address |
|
0x498 |
TRN offset Address |
|
0x499 |
Num Rotor Address |
|
0x49a |
Viterbi Offset Address |
|
0x49b |
Sample collect wait Address |
|
0x49c |
A PHY Control Address |
|
0x49d |
Num Pass Through Address |
|
0x49e |
RX Comp coefficient(s) |
|
0x49f |
cpaRotateValue |
|
0x4a0 |
Sample play count |
|
0x4a1 |
Sample play Buffer Control |
|
0x4a2 |
fourwire Control |
|
0x4a3 |
CPA TailCount Value |
|
0x4a4 |
TX Power Control Cmd |
Bit 15 = TX Power Control Enabled, Bit 14 = Hardware TX Power Control Enabled, Bit 13 = Use TX Power Control Coefficients, Bits 0-6 = Power index |
0x4a5 |
TX Power Control Nnum |
|
0x4a6 |
TX Power Control IdleTssi |
|
0x4a7 |
TX Power Control TargetPower |
|
0x4a8 |
TX Power Control DeltaPower Limit |
|
0x4a9 |
TX Power Control BaseIndex |
|
0x4aa |
TX Power Control Power Index |
|
0x4ab |
TX Power Control Status |
|
0x4ac |
LP RF signal LUT |
|
0x4ad |
RX Radio Control Filter State |
|
0x4ae |
RX Radio Control |
|
0x4af |
NRSSI status Address |
|
0x4b0 |
RF override 2 |
|
0x4b1 |
RF override 2 val |
|
0x4b2 |
PS Control override val0 |
|
0x4b3 |
PS Control override val1 |
|
0x4b4 |
PS Control override val2 |
|
0x4b5 |
TX gain Control override val |
|
0x4b6 |
RX gain Control override val |
|
0x4b7 |
AFE DDFS |
|
0x4b8 |
AFE DDFS pointer init |
|
0x4b9 |
AFE DDFS incr init |
|
0x4ba |
mrcNoiseReduction |
|
0x4bb |
TRLookup3 |
|
0x4bc |
TRLookup4 |
|
0x4bd |
Radar FIFO Status |
|
0x4be |
GPIO Out enable |
|
0x4bf |
GPIO Select |
|
0x4c0 |
GPIO Out |
|
revision 1
TBD
revision 2
Offset |
Meaning |
Notes |
0x4d0 |
PAPD Control |
|
0x503 |
LP PHY Control ? |
Guessed based on TX Power Control Init. |