N PHY Workarounds

As usual, there are a bunch, but they didn't split them up by functionality.

  1. Initialize a 4-element u16 array named aux_adc_vmid_rev7_core0 to 0x8e, 0x96, 0x96, 0x96
  2. Initialize a 4-element u16 array named aux_adc_vmid_rev7_core1 to 0x8f, 0x9f, 0x9f, 0x96
  3. Initialize a 7-element u8 array named rfseq_rx2tx_dlys to 8, 6, 6, 2, 4, 60, 1
  4. Initialize u8 chan_range to 0
  5. If the current Band is 2.4 GHz
    1. Call N PHY Classifier with 1, 1 as arguments

  6. Otherwise (5 GHz band)
    1. Call N PHY Classifier with 1, 0 as arguments

  7. if phyhang_avoid is not zero

    1. Call N PHY Stay In Carrier Search with argument 1 (enable)

  8. Set bits 0x11 in PHY Register 0xB1
  9. If PHY Revision >= 7

    1. If PHY Revision is 7
      1. Set bit 1<<4 to PHY Register 0x221

      2. MaskSet PHY Register 0x160 with mask 0xFF80 and set with 0x20

      3. MaskSet PHY Register 0x160 with mask 0x80FF and set with 0x2700

      4. MaskSet PHY Register 0x161 with mask 0xFF80 and set with 0x2E

      5. MaskSet PHY Register 0x161 with mask 0x80FF and set with 0x3300

      6. MaskSet PHY Register 0x162 with mask 0xFF80 and set with 0x37

      7. MaskSet PHY Register 0x162 with mask 0x80FF and set with 0x3A00

      8. MaskSet PHY Register 0x163 with mask 0xFF80 and set with 0x3C

      9. MaskSet PHY Register 0x163 with mask 0x80FF and set with 0x3E00

      10. MaskSet PHY Register 0x164 with mask 0xFF80 and set with 0x3E

      11. MaskSet PHY Register 0x164 with mask 0x80FF and set with 0x3F00

      12. MaskSet PHY Register 0x165 with mask 0xFF80 and set with 0x40

      13. MaskSet PHY Register 0x165 with mask 0x80FF and set with 0x4000

      14. MaskSet PHY Register 0x166 with mask 0xFF80 and set with 0x40

      15. MaskSet PHY Register 0x166 with mask 0x80FF and set with 0x4000

      16. MaskSet PHY Register 0x167 with mask 0xFF80 and set with 0x40

      17. MaskSet PHY Register 0x167 with mask 0x80FF and set with 0x4000

    2. If PHY Revision <= 8

      1. Write 0x1B0 to PHY Register 0x23F
      2. Write 0x1B0 to PHY Register 0x240
    3. If PHY Revision >= 8

      1. MaskSet PHY Register 0xBD with mask 0xFF00 and set with 0x72

    4. Write N PHY table with ID 8, length 1, offset 0, width 16, and data 2
    5. Write N PHY table with ID 8, length 1, offset 0x10, width 16, and data 2
    6. Read N PHY table with ID 30, length 1, offset 0, width 32, and data tmp
    7. Mask tmp with 0xFFFFFF
    8. Write N PHY table with ID 30, length 1, offset 0, width 32, and data tmp
    9. Write N PHY table with ID 7, length 2, offset 0x15e, width 16, and data {0x10f, 0x10f}
    10. Write N PHY table with ID 7, length 2, offset 0x16e, width 16, and data {0x10f, 0x10f}
    11. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

      1. Call N PHY Set RF Seq with 0, the rx2tx rev3 ipa events array, the rx2tx rev3 ipa delays array, and 9 as arguments

    12. MaskSet PHY Register 0x299 with mask 0x3FFF and set with 0x4000

    13. MaskSet PHY Register 0x29D with mask 0x3FFF and set with 0x4000

    14. Call Nphy_read_lpf_ctl with argument 0x154 and save result as lpf_20

    15. Call Nphy_read_lpf_ctl with argument 0x159 and save result as lpf_40

    16. Call Nphy_read_lpf_ctl with argument 0x152 and save result as lpf_11b

    17. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

      1. If (Radio Revision is 5 AND the BW is 40) OR Radio Revision is 7 or 8
        1. Read Radio Register 0x16B and save in bcap_val
        2. Read Radio Register 0x16A and save in scap_val
        3. Copy scap_val to scap_val_11b
        4. Copy bcap_val to bcap_val_11b
        5. If Radio Revision is 5 AND the BW is 40
          1. Copy scap_val to scap_val_11n_20
          2. Copy bcap_val to bcap_val_11n_20
          3. Set scap_val_11n_40 and bcap_val_11n_40 to 0xC
          4. Set rccal_ovrd to true
        6. Else if Radio Revision is 7 or 8
          1. Set lpf_20 to 4
          2. Set lpf_11b to 1
          3. If this is a 2G channel
            1. Set scap_val_11n_20 and scap_val_11n_20 to 0xC
            2. Set scap_val_11n_40 and scap_val_11n_40 to 0xA
          4. Otherwise
            1. Set scap_val_11n_20 and scap_val_11n_20 to 0x14
            2. Set scap_val_11n_40 and scap_val_11n_40 to 0xF
          5. Set rccal_ovrd to true
    18. Otherwise
      1. If Radio Revision is 5
        1. Set lpf_20 to 1
        2. Set lpf_40 to 3
        3. Read Radio Register 0x16B and save in bcap_val
        4. Read Radio Register 0x16A and save in scap_val
        5. Copy scap_val to scap_val_11b
        6. Copy bcap_val to bcap_val_11b
        7. Set scap_val_11n_20 and scap_val_11n_40 to 0x11
        8. Set bcap_val_11n_20 and bcap_val_11n_40 to 0x13
        9. Set rccal_ovrd to true
    19. If rccal_ovrd is true
      1. Set rx2tx_lut_20_11b to (bcap_val_11b << 8) | (scap_val_11b << 3) | lpf_11b

      2. Set rx2tx_lut_20_11n to (bcap_val_11n_20 << 8) | (scap_val_11n_20 << 3) | lpf_20

      3. Set rx2tx_lut_40_11n to (bcap_val_11n_40 << 8) | (scap_val_11n_40 << 3) | lpf_40

      4. Loop 2 times with index core, start with 0, and increment by 1
        1. Write N PHY table with ID 7, length 1, offset 0x152 + core * 16, width 16, and data rx2tx_lut_20_11b
        2. Write N PHY table with ID 7, length 1, offset 0x153 + core * 16, width 16, and data rx2tx_lut_20_11n
        3. Write N PHY table with ID 7, length 1, offset 0x154 + core * 16, width 16, and data rx2tx_lut_20_11n
        4. Write N PHY table with ID 7, length 1, offset 0x155 + core * 16, width 16, and data rx2tx_lut_40_11n
        5. Write N PHY table with ID 7, length 1, offset 0x156 + core * 16, width 16, and data rx2tx_lut_40_11n
        6. Write N PHY table with ID 7, length 1, offset 0x157 + core * 16, width 16, and data rx2tx_lut_40_11n
        7. Write N PHY table with ID 7, length 1, offset 0x158 + core * 16, width 16, and data rx2tx_lut_40_11n
        8. Write N PHY table with ID 7, length 1, offset 0x159 + core * 16, width 16, and data rx2tx_lut_40_11n
      5. Call N PHY RF Ctrl Override Rev7 with arguments 16, 1, 3, 0, 2

    20. Write 0x3 to PHY Register 0x32F
    21. If Radio Revision is 4 or 6
      1. Call NPHY_Rf_Ctl_Override_Rev7 with arguments 4, 1, 3, 0, 0

    22. If Radio Revision is 3, 4, or 6
      1. Set lvlshift to 0
      2. If SROM Revision >= 8 && Boardflags2 & 0x00020000

        1. Set lvlshift to 1
      3. If lvlshift
        1. Write 0x05 to Radio Register 0x5
        2. Write 0x30 to Radio Register 0x6
        3. Write 0x0 to Radio Register 0x7
        4. Set bit 1 in Radio Register 0x4F
        5. Set bit 1 in Radio Register 0xD4
        6. Set bias to 0x1F
        7. Set conv to 0x6F
        8. Set filt to 0xAA
      4. Otherwise
        1. Set bias to 0x2B
        2. Set conv to 0x7F
        3. Set filt to 0xEE
      5. If in 2G mode
        1. Loop for values of core equal to 0 and 1
          1. If core == 0
            1. Write bias to Radio Register 0x5F
            2. Write conv to Radio Register 0x64
            3. Write filt to Radio Register 0x66
          2. Otherwise
            1. Write bias to Radio Register 0xE8
            2. Write conv to Radio Register 0xE9
            3. Write filt to Radio Register 0xEB
    23. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

      1. If in 2G mode
        1. Set bleed to 0
        2. If Radio Revision is 3, 4, or 6
          1. Set bleed to 0x7F
        3. Loop 2 times with index core, start with 0, and increment with 1
          1. If bleed != 0
            1. If core == 0
              1. Write bleed to Radio Register 0x51
            2. Otherwise
              1. Write bleed to Radio Register 0xD6
        4. If Radio Revision is 3
          1. Loop 2 times with index core, start with 0, and increment with 1
            1. If core is 0
              1. Write 0x13 to Radio Register 0x64
              2. Write 0x1F to Radio Register 0x5F
              3. Write 0xEE to Radio Register 0x66
              4. Write 0x8A to Radio Register 0x59
              5. Write 0x3E to Radio Register 0x80
            2. Otherwise
              1. Write 0x13 to Radio Register 0x69
              2. Write 0x1F to Radio Register 0xE8
              3. Write 0xEE to Radio Register 0xEB
              4. Write 0x8A to Radio Register 0xDE
              5. Write 0x3E to Radio Register 0x105
        5. Else if Radio Revision is 7 or 8
          1. If bw is not 40 MHz
            1. Write 0x14 to Radio Register 0x5F
            2. Write 0x12 to Radio Register 0xE8
          2. Otherwise
            1. Write 0x16 to Radio Register 0x5F
            2. Write 0x16 to Radio Register 0xE8
      2. Otherwise
        1. Set freq to channel frequency in MHz
        2. If ((freq >= 5180) && (freq <= 5230)) OR ((freq >= 5745) && (freq <= 5805)

          1. Write 0xFF to Radio Register 0x7D
          2. Write 0xFF to Radio Register 0xFE
    24. Otherwise
      1. If Radio Revision not 5
        1. Loop 2 times with index core, start with 0, and increment with 1
          1. If core is 0
            1. Write 0x61 to Radio Register 0x5C
            2. Write 0x70 to Radio Register 0x51
          2. Otherwise
            1. Write 0x61 to Radio Register 0xE1
            2. Write 0x70 to Radio Register 0xD6
    25. If Radio Revision is 4
      1. Write N PHY table with ID 8, length 1, offset 0x05, width 16, and data 0x20
      2. Write N PHY table with ID 8, length 1, offset 0x15, width 16, and data 0x20
      3. Loop 2 times with index core, start with 0, and increment with 1
        1. If core is 0
          1. Write 0x00 to Radio Register 0x1A1
          2. Write 0x3F to Radio Register 0x1A2
          3. Write 0x3F to Radio Register 0x1A6
        2. Otherwise
          1. Write 0x00 to Radio Register 0x1A7
          2. Write 0x3F to Radio Register 0x1AB
          3. Write 0x3F to Radio Register 0x1AC
    26. Otherwise
      1. Set bit 0x4 in PHY Register 0xA6
      2. Set bit 0x4 in PHY Register 0x8F
      3. Set bit 0x4 in PHY Register 0xA7
      4. Set bit 0x4 in PHY Register 0xA5
      5. Clear bit 0x01 in PHY Register 0xA6
      6. Set bit 0x1 in PHY Register 0x8F
      7. Clear bit 0x01 in PHY Register 0xA7
      8. Set bit 0x1 in PHY Register 0xA5
      9. Write N PHY table with ID 8, length 1, offset 0x05, width 16, and data 0x0
      10. Write N PHY table with ID 8, length 1, offset 0x15, width 16, and data 0x0
      11. Clear bit 0x4 in PHY Register 0xA6
      12. Clear bit 0x4 in PHY Register 0x8F
      13. Clear bit 0x4 in PHY Register 0xA7
      14. Clear bit 0x4 in PHY Register 0xA5
    27. Write 0x2 to PHY Register 0x6A
    28. Write N PHY table with ID 16, length 1, offset 0x100, width 32, and data 20
    29. Write N PHY table with ID 7, length 2, offset 0x138, width 16, and data {0x11,0x11}
    30. Write N PHY table with ID 7, length 1, offset 0x141, width 16, and data 0x77
    31. Write N PHY table with ID 7, length 3, offset 0x133, width 16, and data {0x77,0x11,0x11}
    32. Write N PHY table with ID 7, length 2, offset 0x146, width 16, and data {0x11,0x11}
    33. Write N PHY table with ID 7, length 1, offset 0x123, width 16, and data 0x77
    34. Write N PHY table with ID 7, length 1, offset 0x12A, width 16, and data 0x77
    35. If BW is not 40 MHz
      1. Write N PHY table with ID 16, length 1, offset 3, width 32, and data 0x18D
      2. Write N PHY table with ID 16, length 1, offset 0x7F, width 32, and data 0x18D
    36. Otherwise
      1. Write N PHY table with ID 16, length 1, offset 3, width 32, and data 0x14D
      2. Write N PHY table with ID 16, length 1, offset 0x7F, width 32, and data 0x14D
    37. Call N PHY Gain Control Workarounds

    38. If using 5G
      1. Set tmp to SPROM PDET_RANGE for 5G
    39. Otherwise
      1. Set tmp to SPROM PDET_RANGE for 2G
    40. If tmp is 0
      1. Call N PHY Get Channel Freq Range with argument 0 and save as chan_range

      2. If chan_range not equal to 0
        1. Set aux_adc_vmid_rev7_core0[3] to 0x70
        2. Set aux_adc_vmid_rev7_core1[3] to 0x70
        3. Set aux_adc_gain_rev7[3] to 2
      3. Otherwise
        1. Set aux_adc_vmid_rev7_core0[3] to 0x80
        2. Set aux_adc_vmid_rev7_core1[3] to 0x80
        3. Set aux_adc_gain_rev7[3] to 3
    41. Else if tmp is 1
      1. If chan_range not equal to 0
        1. Set aux_adc_vmid_rev7_core0[3] to 0x7C
        2. Set aux_adc_vmid_rev7_core1[3] to 0x7C
        3. Set aux_adc_gain_rev7[3] to 2
      2. Otherwise
        1. Set aux_adc_vmid_rev7_core0[3] to 0x8C
        2. Set aux_adc_vmid_rev7_core1[3] to 0x8C
        3. Set aux_adc_gain_rev7[3] to 1
    42. Else if tmp is 2
      1. If this is a 2057 radio
        1. If the Radio Revision is 5, 7, or 8
          1. If chan_range is 0
            1. Set aux_adc_vmid_rev7_core0[3] to 0x8C
            2. Set aux_adc_vmid_rev7_core1[3] to 0x8C
            3. Set aux_adc_gain_rev7[3] to 0
          2. Otherwise
            1. Set aux_adc_vmid_rev7_core0[3] to 0x96
            2. Set aux_adc_vmid_rev7_core1[3] to 0x96
            3. Set aux_adc_gain_rev7[3] to 0
    43. Else if tmp is 3
      1. If chan_range is 0
        1. Set aux_adc_vmid_rev7_core0[3] to 0x89
        2. Set aux_adc_vmid_rev7_core1[3] to 0x89
        3. Set aux_adc_gain_rev7[3] to 0
    44. Else if tmp is 5
      1. If chan_range is not 0
        1. Set aux_adc_vmid_rev7_core0[3] to 0x80
        2. Set aux_adc_vmid_rev7_core1[3] to 0x80
        3. Set aux_adc_gain_rev7[3] to 3
        4. Otherwise
          1. Set aux_adc_vmid_rev7_core0[3] to 0x70
          2. Set aux_adc_vmid_rev7_core1[3] to 0x70
          3. Set aux_adc_gain_rev7[3] to 2
    45. Write N PHY table with ID 8, length 4, offset 0x08, width 16, and data aux_adc_vmid_rev7_core0
    46. Write N PHY table with ID 8, length 4, offset 0x18, width 16, and data aux_adc_vmid_rev7_core1
    47. Write N PHY table with ID 8, length 4, offset 0x0C, width 16, and data aux_adc_gain_rev7_core1
    48. Write N PHY table with ID 8, length 4, offset 0x1C, width 16, and data aux_adc_gain_rev7_core1
  10. Else if PHY revision >= 3

    1. Write 0x1F8 to PHY Register 0x23F
    2. Write 0x1F8 to PHY Register 0x240
    3. Read N PHY table with ID 30, length 1, offset 0, width 32, and data tmp32
    4. Mask tmp with 0xFFFFFF
    5. Write N PHY table with ID 30, length 1, offset 0, width 32, and data tmp32
    6. Write 0x0125 to PHY Register 0x145
    7. Write 0x01B3 to PHY Register 0x146
    8. Write 0x0105 to PHY register 0x147
    9. Write 0x016E to PHY Register 0x148
    10. Write 0x00CD to PHY Register 0x149
    11. Write 0x0020 to PHY Register 0x14A
    12. Write 0x000C to PHY Register 0x38
    13. Write 0x000C to PHY Register 0x2AE
    14. Call N PHY Set RF Seq with 1, the tx2rx rev3 events array, the tx2rx rev3 delays array, and 8 as arguments

    15. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

      1. Call N PHY Set RF Seq with 0, the rx2tx rev3 ipa events array, the rx2tx rev3 ipa delays array, and 9 as arguments

    16. If (hw_phyrxchain != 3) and (hw_phyrxchain != hw_phytxchain)

      1. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

        1. Set element 5 of rx2tx rev3 delays to 59
        2. Set element 6 of rx2tx rev3 delays to 1
        3. Set element 7 of rx2tx rev3 events to 0x1F
      2. Call N PHY Set RF Seq with 0, the rx2tx rev3 events array, the rx2tx rev3 delays array, and 9 as arguments

    17. If the band type is 2 GHz
      1. Write 0x2 to PHY Register 0x6A
    18. Otherwise
      1. Write 0x9C40 to PHY Register 0x6A
    19. Maskset PHY Register 0x294 with mask 0xF0FF and set with 0x0700
    20. If BW is not 40 MHz
      1. Write an N PHY Table with ID 16, length 1, offset 3, width 32, and 0x18D as data
      2. Write an N PHY Table with ID 16, length 1, offset 127, width 32, and 0x18D as data
    21. Otherwise
      1. Write an N PHY Table with ID 16, length 1, offset 3, width 32, and 0x14D as data
      2. Write an N PHY Table with ID 16, length 1, offset 127, width 32, and 0x14D as data
    22. Call N PHY Gain Control Workarounds

    23. Write N PHY Table with ID 8, length 1, offset 0, width 16, and data 2
    24. Write N PHY Table with ID 8, length 1, offset 16, width 16, and data 2
    25. If the band type is 5 GHz
      1. Set range to srom_fem5g.pdetrange

    26. Otherwise
      1. Set range to srom_fem2g.pdetrange

    27. If range is zero
      1. Set vmid to 0xa2, 0xb4, 0xb4, 0x89
      2. Set gain to 0x02, 0x02, 0x02, 0x00
      3. Call N PHY Get Channel Frequency Range with argument 0 and save result in chan_range

      4. Write an N PHY Table with ID 8, length 4, 0ffset 0x08, width 16, and data from vmid
      5. Write an N PHY Table with ID 8, length 4, 0ffset 0x18, width 16, and data from vmid
      6. Write an N PHY Table with ID 8, length 4, 0ffset 0x0C, width 16, and data from gain
      7. Write an N PHY Table with ID 8, length 4, 0ffset 0x1C, width 16, and data from gain
    28. Else if range is 1
      1. Set vmid to 0xb4, 0xb4, 0xb4, 0x24
      2. Set gain to 0x02, 0x02, 0x02, 0x02
      3. Write an N PHY Table with ID 8, length 4, 0ffset 0x08, width 16, and data from vmid
      4. Write an N PHY Table with ID 8, length 4, 0ffset 0x18, width 16, and data from vmid
      5. Write an N PHY Table with ID 8, length 4, 0ffset 0x0C, width 16, and data from gain
      6. Write an N PHY Table with ID 8, length 4, 0ffset 0x1C, width 16, and data from gain
    29. Else if range is 2
      1. Set vmid to 0xa2, 0xb4, 0xb4, 0x74
      2. Set gain to 0x02, 0x02, 0x02, 0x04
      3. If PHY Revision >= 6

        1. Call N PHY Get Channel Freq Range with argument 0 and save as chan_range

        2. If chan_range != 0
          1. Set vmid[3] to 0x8E
        3. Otherwise
          1. Set vmid[3] to 0x94
        4. Set gain[3] to 3
      4. Else if PHY Revision is 5
        1. Set vmid[3] to 0x84
        2. Set gain[3] to 2
      5. Write an N PHY Table with ID 8, length 4, 0ffset 0x08, width 16, and data from vmid
      6. Write an N PHY Table with ID 8, length 4, 0ffset 0x18, width 16, and data from vmid
      7. Write an N PHY Table with ID 8, length 4, 0ffset 0x0C, width 16, and data from gain
      8. Write an N PHY Table with ID 8, length 4, 0ffset 0x1C, width 16, and data from gain
    30. Else if range is 3
      1. Call N PHY Get Channel Freq Range with argument 0 and save as chan_range

      2. If (PHY Revision >= 4) and (chan_range is 0)

        1. Set vmid to 0xa2, 0xb4, 0xb4, 0x270
        2. Set gain to 0x02, 0x02, 0x02, 0x00
        3. Write an N PHY Table with ID 8, length 4, 0ffset 0x08, width 16, and data from vmid
        4. Write an N PHY Table with ID 8, length 4, 0ffset 0x18, width 16, and data from vmid
        5. Write an N PHY Table with ID 8, length 4, 0ffset 0x0C, width 16, and data from gain
        6. Write an N PHY Table with ID 8, length 4, 0ffset 0x1C, width 16, and data from gain
    31. Else if range is 4 or 5
      1. Set vmid to 0xa2, 0xb4, 0xb4, 0x0
      2. Set gain to 0x02, 0x02, 0x02, 0x0
      3. Call N PHY Get Channel Freq Range with argument 0 and save as chan_range

      4. If chan_range is not zero
        1. If range is 4
          1. Set vmid[3] to 0x8e
          2. Set tmp1 to 0x96
          3. Set gain[3] to 0x2
        2. Otherwise
          1. Set vmid[3] to 0x89
          2. Set tmp1 to 0x89
          3. Set gain[3] to 0
      5. Otherwise
        1. If range is 4
          1. Set vmid[3] to 0x89
          2. Set tmp1 to 0x8b
          3. Set gain[3] to 0x2
        2. Otherwise
          1. Set vmid[3] to 0x74
          2. Set tmp1 to 0x70
          3. Set gain[3] to 0
      6. Write an N PHY Table with ID 8, length 4, 0ffset 0x08, width 16, and data from vmid
      7. Write an N PHY Table with ID 8, length 4, 0ffset 0x0C, width 16, and data from gain
      8. Set vmid[3] to tmp1
      9. Write an N PHY Table with ID 8, length 4, 0ffset 0x18, width 16, and data from vmid
      10. Write an N PHY Table with ID 8, length 4, 0ffset 0x1C, width 16, and data from gain
    32. Write 0x00 to Radio Register 0x6043
    33. Write 0x00 to Radio Register 0x7043
    34. Write 0x06 to Radio Register 0x6041
    35. Write 0x06 to Radio Register 0x7041
    36. Write 0x07 to Radio Register 0x6040
    37. Write 0x07 to Radio Register 0x7040
    38. Write 0x88 to Radio Register 0x603D
    39. Write 0x88 to Radio Register 0x703D
    40. Write 0x00 to Radio Register 0x603F
    41. Write 0x00 to Radio Register 0x703F
    42. Write 0x00 to Radio Register 0x6049
    43. Write 0x00 to Radio Register 0x7049
    44. If 5G active
      1. Set triso to SPROM FEM 5G tr_iso
    45. Otherwise
      1. Set triso to SPROM FEM 2G tr_iso
    46. If triso is 7
      1. Call N PHY War Force Trsw Cliplo with argument 0

      2. Call N PHY War Force Trsw Cliplo with argument 1

    47. Call N PHY WAR TX Chain Update with hw_phytxchain as argument

    48. If (boardflags2 & 0x2) and (band type is 5G) or (boardflags2 & 0x400) and (band type is 2G)

      1. Set weight to 0x00088888
    49. Otherwise
      1. Set weight to 0x88888888
    50. Write an N PHY Table with ID 30, length 1, offset 1, width 32, and data weight
    51. Write an N PHY Table with ID 30, length 1, offset 2, width 32, and data weight
    52. Write an N PHY Table with ID 30, length 1, offset 3, width 32, and data weight
    53. If PHY Revision equal 4 and band type is 5G
      1. Write 0x70 to Radio Register 0x2067
      2. Write 0x70 to Radio Register 0x3067
    54. If edcrs_threshold_lock is zero

      1. Write 0x3EB to PHY Register 0x224
      2. Write 0x3EB to PHY Register 0x225
      3. Write 0x341 to PHY Register 0x226
      4. Write 0x341 to PHY Register 0x227
      5. Write 0x42B to PHY Register 0x228
      6. Write 0x42B to PHY Register 0x229
      7. Write 0x381 to PHY Register 0x22A
      8. Write 0x381 to PHY Register 0x22B
      9. Write 0x42B to PHY Register 0x22C
      10. Write 0x43B to PHY Register 0x22D
      11. Write 0x381 to PHY Register 0x22E
      12. Write 0x381 to PHY Register 0x22F
    55. If PHY Revision >= 6

      1. If boardflags2 & 0x1000

        1. Call Mhf with arguments 3, 0x80, 0x80, 3 as arguments

  11. Otherwise
    1. If (boardflags2 & 0x100) OR (boardtype is 0x8B)

      1. Set the 7 element u8 array rfseq_rx2tx_dlys to 1, 6, 6, 2, 4, 20, 1
    2. If this is a 5G channel AND phy_5g_pwrgain is true

      1. Clear bit 8 in Radio register 0x86
      2. Clear bit 8 in Radio register 0xB5
    3. Otherwise
      1. Set bit 0x8 in Radio register 0x86
      2. Set bit 0x8 in Radio register 0xB5
    4. Write an N PHY Table with ID 8, length 1, offset 0, width 16, and data 0x000A
    5. Write an N PHY Table with ID 8, length 1, offset 0x10, width 16, and data 0x000A
    6. If PHY Revision < 3

      1. Write an N PHY Table with ID 8, length 1, offset 0x02, width 16, and data 0xCDAA
      2. Write an N PHY Table with ID 8, length 1, offset 0x12, width 16, and data 0xCDAA
    7. If PHY Revision < 2

      1. Write an N PHY Table with ID 8, length 1, offset 0x08, width 16, and data 0x0000
      2. Write an N PHY Table with ID 8, length 1, offset 0x18, width 16, and data 0x0000
      3. Write an N PHY Table with ID 8, length 1, offset 0x07, width 16, and data 0x7AAB
      4. Write an N PHY Table with ID 8, length 1, offset 0x17, width 16, and data 0x7AAB
      5. Write an N PHY Table with ID 8, length 1, offset 0x06, width 16, and data 0x0800
      6. Write an N PHY Table with ID 8, length 1, offset 0x16, width 16, and data 0x0800
    8. Write 0x02D8 to PHY Register 0xF8
    9. Write 0x0301 to PHY Register 0xF9
    10. Write 0x02D8 to PHY Register 0xFA
    11. Write 0x0301 to PHY Register 0xFB
    12. Call N PHY Set RF Sequence with 0, events, delays, and 7 as arguments

    13. Set events to 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8
    14. Set delays to 8, 6, 2, 4, 4, 6, 1
    15. Call N PHY Set RF Sequence with 1, events, delays, and 7 as arguments

    16. Call N PHY Workarounds Gain Control

    17. If PHY Revision < 2

      1. If PHY Register 0xA0 & 0x02

        1. Call Mhf with arguments 2, 0x10, 0x10, 3 as arguments

    18. Else if the PHY Revision is 2
      1. Write 0 to PHY Registers 0x1E3 and 0x1E4
    19. If PHY Revision < 2

      1. Clear bit 0x0080 in PHY Register 0x90
    20. Write 293 to PHY Register 0x145
    21. Write 435 to PHY Register 0x146
    22. Write 261 to PHY Register 0x147
    23. Write 366 to PHY Register 0x148
    24. Write 205 to PHY Register 0x149
    25. Write 32 to PHY Register 0x14A
    26. If PHY Revision < 3

      1. Maskset PHY Register 0x142 with mask 0x0FFF and set with 0
      2. Write 0xB5 to PHY Register 0x192
      3. Write 0xA4 to PHY Register 0x193
      4. Write 0x00 to PHY Register 0x194
    27. if PHY Revision is 2
      1. Set bit 0x8 in PHY Register 0x221
  12. If phyhang_avoid is not zero

    1. Call N PHY Stay in Carrier Search with argument 0 (disable)

802.11/PHY/N/Workarounds (last edited 2012-07-24 22:46:11 by lwfinger)