N PHY Gain Control Workaround
- Initialize a 6-element u8 array lpf_gain_db to 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12
- Initialize a 6-element u8 array lpf_gainbits to 0, 1, 2, 3, 3, 3
- If this is a 5G channel
- Set triso tp SPROM FEM 5G TRISO
- Otherwise
- Set triso tp SPROM FEM 2G TRISO
If PHY Revision >= 7
- If Radio Revision is 5
- Else if Radio Revision is 7
- Maskset PHY Register 0x283 with mask 0xFF00 and set with 0x44
- Maskset PHY Register 0x280 with mask 0xFF00 and set with 0x44
- Else if Radio Revision is 3 or 8
- If Radio Revision is 8
- Maskset PHY Register 0x283 with mask 0xFF00 and set with 0x44
- Maskset PHY Register 0x280 with mask 0xFF00 and set with 0x44
- Otherwise
Else if PHY Revision >= 3
- Set bit 0x0040 in PHY Register 0xA0
- Set bit 0x2000 in PHY Register 0x1C
- Set bit 0x2000 in PHY Register 0x32
- Read PHY Register 0x09 and mask with 0x0001
- If the result is 0
If PHY Revision >= 6
- If Radio Revision equals 11
- Set lna1_gain_db to contain 10, 14, 19, 27
- Set lna2_gain_db to contain -5, 6, 10, 15
- Set rfseq_init_gain to contain 0x413f, 0x413f
- Set init_gaincode to 0x427E
- Set clip1hi_gaincode to 0x007e
- Set clip1lo_gaincode to 0x1074
- Set nbclip_th to 0x1d0
- Set w1clip_th to 5
- Set crsmin_th to 0x18
- Set crsminl_th to 0x18
- Set crsminl_th to 0x18
- Set crsminu_th to 0x18
- Set rssi_gain to 0x50
- Otherwise
- Set lna1_gain_db to contain 8, 13, 18, 25
- Set lna2_gain_db to contain -5, 6, 10, 14
If boardflags & 0x1000 is not zero
- Set rfseq_init_gain to 0x113f, 0x113f
- Set init_gaincode to 0x127e
- Otherwise
- Set rfseq_init_gain to 0x513f, 0x513f
- Set init_gaincode to 0x527e
- Set clip1hi_gaincode to 0x1076
- If triso is 0
- Set clip1lo_gaincode to 0x0062
- Else if triso is 1
- Set clip1lo_gaincode to 0x0064
- Else if triso is 2
- Set clip1lo_gaincode to 0x006a
- Else if triso is 3
- Set clip1lo_gaincode to 0x106a
- Else if triso is 4
- Set clip1lo_gaincode to 0x106c
- Else if triso is 5
- Set clip1lo_gaincode to 0x1074
- Else if triso is 6
- Set clip1lo_gaincode to 0x107c
- Else if triso is 7
- Set clip1lo_gaincode to 0x207c
- Otherwise
- Set clip1lo_gaincode to 0x106a
- Set nbclip_th to 0x1d0
- Set w1clip_th to 9
- Set crsmin_th to 0x18
- Set crsminl_th to 0x18
- Set crsminu_th to 0x18
- Set rssi_gain to 0x50
- If Radio Revision equals 11
- Else if PHY Revision is 5
- Set lna1_gain_db to 9, 13, 18, 26
- Set lna2_gain_db to-3, 7, 11, 16
If boardflags & 0x1000 is not zero
- Set rfseq_init_gain to 0x013f, 0x013f, 0x013f, 0x013f
- Set init_gaincode to 0x027e
- Otherwise
- Set rfseq_init_gain to 0x413f, 0x413f, 0x413f, 0x413f
- Set init_gaincode to 0x427e
- Set clip1hi_gaincode to 0x1076
- If triso is 0
- Set clip1lo_gaincode to 0x0062
- Else if triso is 1
- Set clip1lo_gaincode to 0x0064
- Else if triso is 2
- Set clip1lo_gaincode to 0x006a
- Else if triso is 3
- Set clip1lo_gaincode to 0x106a
- Else if triso is 4
- Set clip1lo_gaincode to 0x106c
- Else if triso is 5
- Set clip1lo_gaincode to 0x1074
- Else if triso is 6
- Set clip1lo_gaincode to 0x107c
- Else if triso is 7
- Set clip1lo_gaincode to 0x207c
- Otherwise
- Set clip1lo_gaincode to 0x106a
- Set nbclip_th to 0x1d0
- Set w1clip_th to 9
- Set crsmin_th to 0x18
- Set crsminl_th to 0x18
- Set crsminu_th to 0x18
- Set rssi_gain to 0x50
- Else if PHY Revision is 4
- Set lna1_gain_db to 8, 12, 17, 25
- Set lna2_gain_db to -5, 6, 10, 14
- Set rfseq_init_gain to 0x513f, 0x513f, 0x513f, 0x513f
- Set init_gaincode to 0x527e
- Set clip1hi_gaincode to 0x007e
- Set clip1lo_gaincode to 0x0074
- Set nbclip_th to 0x1a1
- Set w1clip_th to 5
- Set crsmin_th to 0x18
- Set crsminl_th to 0x18
- Set crsminu_th to 0x18
- Set rssi_gain to 0x50
- Otherwise
- Set lna1_gain_db to 7, 11, 16, 23
- Set lna2_gain_db to -5, 6, 10, 14
- Set rfseq_init_gain to 0x613f, 0x613f, 0x613f, 0x613f
- Set init_gaincode to 0x627e
- Set clip1hi_gaincode to 0x107e
- Set clip1lo_gaincode to 0x0074
- Set nbclip_th to 0x1a1
- Set w1clip_th to 5
- Set crsmin_th to 0x18
- Set crsminl_th to 0x18
- Set crsminu_th to 0x18
- Set rssi_gain to 0x50
- Set tia_gain_db to 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A
- Set tia_gainbits to 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03
- Set clip1md_gaincode to 0x0066
- Otherwise
If PHY Revision >= 6
- Set lna1_gain_db to 6, 10, 16, 21
- Set lna2_gain_db to -7, 0, 4, 8
- Set tia_gain_db to 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d
- Set tia_gainbits to 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04
- Set rfseq_init_gain to 0x714f, 0x714f
- Set init_gaincode to 0x729e
- Set clip1hi_gaincode to 0x029e
- Set clip1md_gaincode to 0x2084
- Set clip1lo_gaincode to 0x2086
- Set crsmin_th to 0x24
- Set crsminl_th to 0x24
- If Radio Revision equals 11 and thes is not a 40 MHZ channel
- Set crsminu_th to 0x2d
- Otherwise
- Set crsminu_th to 0x24
- Set nbclip_th to 0x0f0
- Set rssi_gain to 0x90
- Else if PHY Revision is 5
- Set lna1_gain_db to 6, 10, 16, 21
- Set lna2_gain_db to -7, 0, 4, 8
- Set tia_gain_db to 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d
- Set tia_gainbits to 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04
- Set rfseq_init_gain to 0x714f, 0x714f, 0x714f, 0x714f
- Set init_gaincode to 0x729e
- Set clip1hi_gaincode to 0x029e
- Set clip1md_gaincode to 0x2084
- Set clip1lo_gaincode to 0x2086
- Set crsmin_th to 0x24
- Set crsminl_th to 0x24
- Set crsminu_th to 0x2d
- Set nbclip_th to 0x0a9
- Set rssi_gain to 0x90
- Else if PHY Revision is 4
- Set lna1_gain_db to 8, 12, 18, 23
- Set lna2_gain_db to -5, 2, 6, 10
- Set tia_gain_db to 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d
- Set tia_gainbits to 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04
If boardflags & 0x10000000 is not zero
- Set rfseq_init_gain to 0x314f, 0x314f, 0x314f, 0x314f
- Set init_gaincode to 0x329e
- Otherwise
- Set rfseq_init_gain to 0x614f, 0x614f, 0x614f, 0x614f
- Set init_gaincode to 0x629e
- Set clip1hi_gaincode to 0x029e
- Set clip1md_gaincode to 0x1084
- Set clip1lo_gaincode to 0x0086
- Set crsmin_th to 0x24
- Set crsminl_th to 0x24
- Set crsminu_th to 0x2d
- Set nbclip_th to 0x0a9
- Set rssi_gain to 0x90
- Otherwise
- Set lna1_gain_db to 7, 11, 17, 23
- Set lna2_gain_db to -6, 2, 6, 10
- Set tia_gain_db to 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13
- Set tia_gainbits to 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06
- Set rfseq_init_gain to 0x516f, 0x516f, 0x516f, 0x516f
- Set init_gaincode to 0x52de
- Set clip1hi_gaincode to 0x00de
- Set clip1md_gaincode to 0x00ca
- Set clip1lo_gaincode to 0x00cc
- Set crsmin_th to 0x1e
- Set crsminl_th to 0x1e
- Set crsminu_th to 0x1e
- Set nbclip_th to 0x1a1
- Set rssi_gain to 0x50
- Set w1clip_th to 25
- Write 0x17 to PHY Register 0x6037
- Write 0x17 to PHY Register 0x7037
- Write 0xF0 to PHY Register 0x6038
- Write 0xF0 to PHY Register 0x7038
- Write rssi_gain to PHY Register 0x6029
- Write rssi_gain to PHY Register 0x7029
- Write 0x17 to PHY Register 0x6030
- Write 0x17 to PHY Register 0x7030
- Write 0xFF to PHY Register 0x6031
- Write 0xFF to PHY Register 0x7031
- Write an N PHY Table with ID 0, length 4, offset 8, width 8, and data from lna1_gain_db
- Write an N PHY Table with ID 1, length 4, offset 8, width 8, and data from lna1_gain_db
- Write an N PHY Table with ID 0, length 4, offset 16, width 8, and data from lna2_gain_db
- Write an N PHY Table with ID 1, length 4, offset 16, width 8, and data from lna2_gain_db
- Write an N PHY Table with ID 0, length 10, offset 32, width 8, and data from tia_gain_db
- Write an N PHY Table with ID 1, length 10, offset 32, width 8, and data from tia_gain_db
- Write an N PHY Table with ID 2, length 10, offset 32, width 8, and data from tia_gainbits
- Write an N PHY Table with ID 3, length 10, offset 32, width 8, and data from tia_gainbits
- Write an N PHY Table with ID 0, length 6, offset 0x40, width 8, and data from lpf_gain_db
- Write an N PHY Table with ID 1, length 6, offset 0x40, width 8, and data from lpf_gain_db
- Write an N PHY Table with ID 2, length 6, offset 0x40, width 8, and data from lpf_gainbits
- Write an N PHY Table with ID 3, length 6, offset 0x40, width 8, and data from lpf_gainbits
- Write init_gaincode to PHY register 0x20
- Write init_gaincode to PHY register 0x2A7
- Write an N PHY Table with ID 7, length 2, offset 0x106, width 16, and data from rfseq_init_gain
- Write clip1hi_gaincode to PHY Register 0x22
- Write clip1hi_gaincode to PHY Register 0x2A9
- Write clip1md_gaincode to PHY Register 0x24
- Write clip1md_gaincode to PHY Register 0x2AB
- Write clip1lo_gaincode to PHY Register 0x37
- Write clip1lo_gaincode to PHY Register 0x2AD
MaskSet PHY Register 0x27D with mask 0xFF00 and set with crsmin_th
MaskSet PHY Register 0x280 with mask 0xFF00 and set with crsminl_th
MaskSet PHY Register 0x283 with mask 0xFF00 and set with crsminu_th
- Write nbclip_th to PHY Register 0x2B
- Write nbclip_th to PHY Register 0x41
MaskSet PHY Register 0x27 with mask 0xFFC0 and set with w1clip_th
MaskSet PHY Register 0x3D with mask 0xFFC0 and set with w1clip_th
- Write 0x809C to PHY Register 0x150
- Otherwise
MaskSet PHY Register 0x1C with mask 0xDFFF and set with 0x2000
MaskSet PHY Register 0x32 with mask 0xDFFF and set with 0x2000
- Write 0x84 to PHY Register 0x2B
- Write 0x84 to PHY Register 0x41
- If the band width is 20 MHz
- Write 0x002B to PHY Register 0x6B
- Write 0x002B to PHY Register 0x6C
- Write 0x0009 to PHY Register 0x6D
- Write 0x0009 to PHY Register 0x6E
MaskSet PHY Register 0x27 with mask 0xFFC0 and set with 21
MaskSet PHY Register 0x3D with mask 0xFFC0 and set with 21
- If the band width is 20 MHz
- Write 0x809C to PHY Register 0x150
If nphy_gain_boost is not zero
- If the band is 2 GHz and the band width is 40 MHz
- Set code to 4
- Otherwise
- Set code to 5
- If the band is 2 GHz and the band width is 40 MHz
- Otherwise
- If the band width is 40 MHz
- Set code to 6
- Otherwise
- Set code to 7
- If the band width is 40 MHz
MaskSet PHY Register 0x20 with mask 0xF07F and set with code << 7
MaskSet PHY Register 0x36 with mask 0xF07F and set with code << 7
- Write 0x1D06 to PHY Register 0x72
- Loop 4 times with ctr as index
Set regval[ctr] to (code << 8) | 0x7C
- Write an N PHY Table with ID 7, length 4, offset 0x106, width 16, and data from regval
If nphy_elna_gain_config is not zero
- Set regval to 0, 1, 1, 1
- Write an N PHY Table with ID 2, length 4, offset 8, width 16, and data from regval
- Write an N PHY Table with ID 3, length 4, offset 8, width 16, and data from regval
- Loop 4 times with index ctr
Set regval[ctr] to (code << 8) | 0x74
- Write an N PHY Table with ID 7, length 4, offset 0x106, width 16, and data from regval
- If PHY Revision is 2
- Write 0x20 to PHY Register 0x72
- Loop 21 times with index starting at 0
- Set regval[index] to 3 * index
- Write an N PHY Table with ID 0, length 21, offset 32, width 16, and data from regval
- Write an N PHY Table with ID 1, length 21, offset 32, width 16, and data from regval
- Loop 21 times with index starting at 0
- Set regval[index] to index
- Write an N PHY Table with ID 2, length 21, offset 32, width 16, and data from regval
- Write an N PHY Table with ID 3, length 21, offset 32, width 16, and data from regval
- Preset an array called rfseq_events with 6, 8, 7
- Preset an array called rfseq_delays with 10, 30, 1
Call N PHY Set RF Seq with 5, rfseq_events, rfseq_delays, 3 as arguments
MaskSet PHY Register 0x153 with mask 0x00FF and set with 0x5A00
- If the current band is 2 GHz
MaskSet PHY Register 0xC5D with mask 0xFF80 and set with 4