init routine
- turn off interrupts
do initial PHY calibration
do Backplane timeout fixup
- reset PSM by setting the MAC control register to "IHR Region Enabled" | "PSM Jump 0"
- upload firmware (see below)
- upload PCM microcode (see below)
- set all MAC interrupt register bits and start PSM by writing "Infra Mode" | "IHR Region Enabled" | "PSM Run" to the MAC control register
- wait (up to one second) until MAC suspended is set in the MAC interrupt register
- initialise GPIOs (to be detailed)
- write core dependent initial values (see below)
fix up FIFO sizes if necessary
validate that FIFO sizes in SHM match expectations
- set default antenna swap threshold value in SHM
- initialise PIO
- invalidate the last posted broadcast/multicast frame ID in the SHM (by writing 0xffff)
- update slot timings
- initialise FIFO interrupts
- allow MAC to control PHY clock (by setting the "MAC PHY Clock Control Enable" bit in the TM State Low register)
if core revision is >= 5, program the dynamic clock control faster powerup delay (to be detailed)
- write core revision to SHM
- write retry limits to microcode registers
- write rate fallback retry limits to SHM
- set MAC address and BSSID
clear crypto engine
- initialise DMA engines/PIO
initialise band
- enable MAC
firmware
Upload the corresponding microcode according to this table:
core revision |
microcode |
15 |
d11ucode15 |
14 |
d11ucode14 |
13 |
d11ucode13 |
11-12 |
d11ucode11 |
9 |
d11ucode9 |
5-8, 10 |
d11ucode5 |
4 |
d11ucode4 |
PCM microcode
Upload the corresponding PCM microcode according to this table:
core revision |
microcode |
4 |
d11pcm4 |
5-10 |
d11pcm5 |
>= 11 |
- |
initial values
Upload the corresponding initial values according to this table:
core revision |
PHY |
initial values |
15 |
LP |
d11lp0initvals15 |
14 |
LP |
d11lp0initvals14 |
13 |
A |
d11a0g1initvals13 |
13 |
G |
d11b0g0initvals13 |
13 |
LP |
d11lp0initvals13 |
11-12 |
N |
d11n0initvals11 |
9 |
A |
d11a0g1initvals9 (2.4 GHz PHY available) or d11a0g0initvals9 (no 2.4 GHz PHY) |
9 |
G |
d11b0g0initvals9 |
5-8, 10 |
A |
d11a0g1initvals5 (2.4 GHz PHY available) or d11a0g0initvals5 (no 2.4 GHz PHY) |
5-8, 10 |
G |
d11b0g0initvals5 |
4 |
A |
d11a0g0initvals4 |
4 |
G |
d11b0g0initvals4 |