expected FIFO sizes
FIFO sizes are always given in blocks of 256 bytes, below as well as in the SHM registers.
FIFOs start at 6 blocks into the core's address space.
revision 4 and below
The first 5 FIFOs are 15, the 6th 2 blocks by default, this makes a total of 92 blocks. But this is probably wrong since only FIFO 0 and 2 are used...
revision 5 through 8
The FIFOs are 9, 13, 10, 8, 13 and 1 blocks by default, a total of 54 blocks.
revision 9 and up (to 11)
The FIFOs are 10, 14, 11, 9, 14 and 2 blocks by default, a total of 60 blocks.
revision 9 and 10 fixup
802.11 cores with revisions 9 and 10 have larger FIFO sizes, but run with the same microcode as revision 5 and higher, hence the microcode is unaware of the larger FIFOs. This shouldn't hurt, but can be fixed up as follows. The fixup is only possible on rev 9 and higher.
For each FIFO:
reset FIFO (write 1<<15 into the Transmit FIFO Command register) ORed with the FIFO number shifted up by 8
- write FIFO definition word to the Transmit FIFO Def register
- reset FIFO again
Also, you need to update the SHM TX FIFO Size values!
The FIFO definition word is defined as follows:
last block of FIFO
first block of FIFO
Note that you have a total of 60 blocks and can allocate them as you wish, see above for the defaults.