The SPROM is uint16 based and all reads and writes to the SPROM should be done in 16 bit transactions. The SPROM is accessed through the Backplane Registers, starting at offset 0x1000 for Chipcommon Revision < 31, and 0x0800 for higher revisions. Offsets given here are byte offsets from the beginning of the SPROM. As an example, il0macaddr is found at Backplane Register offset + 0x48 (0x1048 or 0x0848). Unprogrammed values default to 0xFFFF.
SPROM Layouts
For versions 1-3, the SPROM size is 128 bytes. For versions 4, 5 and 8, the size is 440 bytes. Versions 6 and 7 have not been seen. The maximum possible SPROM size is 512 bytes.
For SPROM versions 1-3, the layout may be determined by reading 128 bytes and checking the CRC8. If it passes, the SPROM Revision is found at offset 0x7E. If it doesn't pass the CRC8, it may be SPROM version 4 or higher with special signature values that may be checked to determine the version. An equally valid method is to read 440 bytes and check the CRC8. If it passes this test, the revision is found at offset 0x1B6, otherwise, the contents are invalid.
Revision 1 SPROM
Offset |
Size |
Usage |
Notes |
0x04 |
2 |
Subsytem product ID for PCI |
|
0x06 |
2 |
Subsystem vendor ID for PCI |
|
0x08 |
2 |
Product ID for PCI |
|
Named Parameter Area |
|||
0x48 |
6 |
il0macaddr - MAC address for 802.11b/g |
|
0x4E |
6 |
et0macaddr - MAC address for ethernet |
See b44 Driver |
0x54 |
6 |
et1macaddr - MAC address for 802.11a |
|
Ethernet PHY settings: one or two singles or a dual (encoded bitwise), see b44 Driver |
|||
0x5A |
2 |
bits 4-0: et0phyaddr - MII Address for enet0 |
0x1F if not present |
bits 9-5: et1phyaddr - MII Address for enet1 |
0x1F if not present |
||
bit 14: et0mdcport - MDIO for enet0 |
|
||
bit 15: et1mdcport - MDIO for enet1 |
|
||
Board revision, Antennas 0/1, Country Code |
|||
0x5C |
2 |
bits 7-0: Board Revision |
|
bits 11-8: Country Code |
|
||
bits 13-12: Bitfield of antennas available for A PHY |
|
||
bits 15-14: Bitfield of antennas available for B/G PHY |
|
||
0x5E |
2 |
pa0b0 |
|
0x60 |
2 |
pa0b1 |
|
0x62 |
2 |
pa0b2 |
|
0x64 |
2 |
GPIO 0 and 1 |
See GPIO below |
0x66 |
2 |
GPIO 2 and 3 |
See GPIO below |
PA Max Power (Units: 4*dBm (dBm in Q5.2)) |
|||
0x68 |
2 |
bits 7-0: A PHY Max Power |
|
bits 15-8: B/G PHY Max Power |
|
||
0x6A |
2 |
pa1b0 |
|
0x6C |
2 |
pa1b1 |
|
0x6E |
2 |
pa1b2 |
|
Idle TSSI Target |
|||
0x70 |
2 |
bits 7-0: A PHY |
|
bits 15-8: B/G PHY |
|
||
0x72 |
2 |
Low 16 bits of Board Flags |
If unset (0xFFFF) use 0 |
Antenna Gain If unset, use 2 dBm, all values are in dBm |
|||
0x74 |
2 |
bits 7-0: A PHY |
|
bits 15-8: B/G PHY |
|
||
0x76 |
8 |
OEM String |
SROM Rev 1 only |
SPROM Checksum and Revision |
|||
0x7E |
2 |
bits 7-0: SPROM Revision |
|
bits 15-8: SPROM CRC8 |
|
Revision 2 SPROM
Same as Revision 1 unless specified here
Offset |
Size |
Usage |
Notes |
0x38 |
2 |
High 16 bits of BoardFlags |
|
A PHY Max Power |
|||
0x3A |
2 |
bits 7-0: Max Power High |
|
bits 15-8: Max Power Low |
|
||
0x3C |
2 |
pa1lob0: A PHY PA Low Settings |
|
0x3E |
2 |
pa1lob1: A PHY PA Low Settings |
|
0x40 |
2 |
pa1lob2: A PHY PA Low Settings |
|
0x42 |
2 |
pa1hib0: A PHY PA High Settings |
|
0x44 |
2 |
pa1hib1: A PHY PA High Settings |
|
0x46 |
2 |
pa1hib2: A PHY PA High Settings |
|
Antenna Gain |
|||
0x74 |
2 |
bits 7-0: A PHY |
|
bits 15-8: B/G PHY |
|
||
opo: OFDM Power Offset from CCK Level |
|||
0x78 |
2 |
bits 7-0: OFDM Power Offset from CCK Level |
|
bits 15-8: Unused |
|
||
0x7C |
2 |
Country Code |
2 Characters, 0 if unset |
Antenna gain is stored with granularity of 0.25 dBm as follows:
Mask |
Value |
0xC0 |
Fractional part, this many quarter dBm (unsigned) |
0x3F |
Whole dBm part (signed) |
So, the stored value is found by: Whole + Fractional/4.
Revision 3 SPROM
Same as Revision 2 unless specified here
Offset |
Size |
Usage |
Notes |
0x2C |
4 |
ofdmapo: A PHY OFDM middle subband Power Offset |
Big-Endian |
0x30 |
4 |
ofdmalpo: A PHY OFDM low subband Power Offset |
Big-Endian |
0x34 |
4 |
ofdmahpo: A PHY OFDM high subband Power Offset |
Big-Endian |
GPIO LED Powersave Duty Cycle (Big-Endian) |
|||
0x42 |
4 |
bits 31-24: On Count |
|
bits 23-16: Unused |
|
||
bits 15-8: Off Count |
|
||
bits 7-0: Unused |
|
||
cckpo - CCK Power Offset |
|||
0x78 |
2 |
bits 3-0: CCK Rate 1M Power Offset |
|
bits 7-4: CCK Rate 2M Power Offset |
|
||
bits 11-8: CCK Rate 5.5M Power Offset |
|
||
bits 15-12: CCK Rate 11M Power Offset |
|
||
0x7A |
4 |
ofdmgpo - G PHY OFDM Power Offset, consists of 8 4-bit values for the OFDM bitrates starting 6M in the least significant nibble |
Big-Endian |
Revision 4 SPROM
This revision does not inherit from older layouts
Offset |
Size |
Usage |
Notes |
0x0004 |
2 |
Subsytem product ID for PCI |
|
0x0006 |
2 |
Subsystem vendor ID for PCI |
|
0x0008 |
2 |
Product ID for PCI |
|
0x0040 |
2 |
SPROM Signature |
Must be 0x5372 to be a valid v4 SPROM |
0x0042 |
2 |
Board Revision |
|
0x0044 |
4 |
|
|
0x0048 |
4 |
|
|
0x004C |
6 |
MAC Address |
|
0x0052 |
2 |
Country Code |
Two characters |
0x0054 |
2 |
Regulatory(?) Revision |
|
0x0056 |
1 |
LED 0 Behaviour |
|
0x0057 |
1 |
LED 1 Behaviour |
|
0x0058 |
1 |
LED 2 Behaviour |
|
0x0059 |
1 |
LED 3 Behaviour |
|
0x005A |
2 |
bits 15-8: LED Powersave Duty Cycle |
On Count (value is right shifted by 24) |
bits 7-0: LED Powersave Duty Cycle |
Off Count (value is right shifted by 8) |
||
0x005C |
2 |
bits 7-0: 802.11B/G Antennas Available |
Bitfield |
bits 15-8: 802.11A Antenas Available |
Bitfield |
||
0x005E |
1 |
Antenna 0 Gain |
|
0x005F |
1 |
Antenna 1 Gain |
|
0x0060 |
1 |
Antenna 2 Gain |
|
0x0061 |
1 |
Antenna 3 Gain |
|
Fixed Power Indices when Power Control is disabled |
|||
0x0062 |
2 |
TX Power Index 2GHz |
|
0x0064 |
2 |
TX Power Index 2GHz |
|
0x0066 |
2 |
TX Power Index 5GHz middle subband |
|
0x0068 |
2 |
TX Power Index 5GHz middle subband |
|
0x006A |
2 |
TX Power Index 5GHz low subband |
|
0x006C |
2 |
TX Power Index 5GHz low subband |
|
0x006E |
2 |
TX Power Index 5GHz high subband |
|
0x0070 |
2 |
TX Power Index 5GHz high subband |
|
Per Path Variables |
|||
0x0080 |
- |
Path 1 Variables |
|
0x00AE |
- |
Path 2 Variables |
|
0x00DC |
- |
Path 3 Variables |
|
0x010A |
- |
Path 4 Variables |
|
Power Offsets |
|||
0x0138 |
2 |
2GHz CCK Power Offset |
|
0x013A |
4 |
2GHz OFDM Power Offset |
|
0x013E |
4 |
5GHz middle subband OFDM Power Offset |
|
0x0142 |
4 |
5GHz low subband OFDM Power Offset |
|
0x0146 |
4 |
5GHz high subband OFDM Power Offset |
|
0x014A |
2 |
2GHz MCS Power Offset |
They may have reserved space for additional values |
0x015A |
2 |
5GHz MCS Power Offset |
They may have reserved space for additional values |
0x016A |
2 |
5GHz low subband MCS Power Offset |
They may have reserved space for additional values |
0x017A |
2 |
5GHz high subband MCS Power Offset |
They may have reserved space for additional values |
0x018A |
2 |
CCD Power Offset |
|
0x018C |
2 |
STBC Power Offset |
|
0x018E |
2 |
BW40 Power Offset |
|
0x0190 |
2 |
BWDUP Power Offset |
|
0x01B6 |
2 |
bits 7-0: SROM Revision |
|
Path Variables
Offsets are given as byte offsets from the start of the Path Variable section.
Offset |
Size |
Function |
Notes |
0x0000 |
2 |
bits 7-0: Max Power 2GHz |
|
bits 15-8: ITT 2GHz |
|
||
0x0002 |
2 |
2GHz Power Amplifier W0 |
|
0x0004 |
2 |
2GHz Power Amplifier W1 |
|
0x0006 |
2 |
2GHz Power Amplifier W2 |
|
0x0008 |
2 |
2GHz Power Amplifier W3 |
|
0x000A |
2 |
bits 7-0: Max Power 5GHz |
|
bits 15-8: ITT 5GHz |
|
||
0x000C |
1 |
5GHz high subband Power Amplifier Max |
|
0x000D |
1 |
5GHz low subband Power Amplifier Max |
|
5 GHz Power Amplifier |
|||
0x000E |
2 |
5GHz Power Amplifier (middle subband) |
|
0x0010 |
2 |
5GHz Power Amplifier (middle subband) |
|
0x0012 |
2 |
5GHz Power Amplifier (middle subband) |
|
0x0014 |
2 |
5GHz Power Amplifier (middle subband) |
|
0x0016 |
2 |
5GHz Power Amplifier (low subband) |
|
0x0018 |
2 |
5GHz Power Amplifier (low subband) |
|
0x001A |
2 |
5GHz Power Amplifier (low subband) |
|
0x001C |
2 |
5GHz Power Amplifier (low subband) |
|
0x001E |
2 |
5GHz Power Amplifier (high subband) |
|
0x0020 |
2 |
5GHz Power Amplifier (high subband) |
|
0x0022 |
2 |
5GHz Power Amplifier (high subband) |
|
0x0024 |
2 |
5GHz Power Amplifier (high subband) |
|
Revision 5 SPROM
Same as Revision 4 unless specified here
Offset |
Size |
Usage |
Notes |
0x0004 |
2 |
Subsytem product ID for PCI |
|
0x0006 |
2 |
Subsystem vendor ID for PCI |
|
0x0008 |
2 |
Product ID for PCI |
|
0x0042 |
2 |
Board Revision |
|
0x004A |
4 |
|
|
0x004E |
4 |
|
|
0x0052 |
6 |
MAC Address |
|
0x0044 |
2 |
Country Code |
Two characters |
0x0046 |
2 |
Regulatory(?) Revision |
|
0x0076 |
1 |
LED 0 Behaviour |
|
0x0077 |
1 |
LED 1 Behaviour |
|
0x0078 |
1 |
LED 2 Behaviour |
|
0x0079 |
1 |
LED 3 Behaviour |
|
0x005A |
2 |
bits 15-8: LED Powersave Duty Cycle |
On Count (value is right shifted by 24) |
bits 7-0: LED Powersave Duty Cycle |
Off Count (value is right shifted by 8) |
||
0x005C |
2 |
bits 7-0: 802.11B/G Antennas Available |
Bitfield |
bits 15-8: 802.11A Antenas Available |
Bitfield |
||
0x005E |
1 |
Antenna 0 Gain |
|
0x005F |
1 |
Antenna 1 Gain |
|
0x0060 |
1 |
Antenna 2 Gain |
|
0x0061 |
1 |
Antenna 3 Gain |
|
Fixed Power Indices when Power Control is disabled |
|||
0x0062 |
2 |
TX Power Index 2GHz |
|
0x0064 |
2 |
TX Power Index 2GHz |
|
0x0066 |
2 |
TX Power Index 5GHz middle subband |
|
0x0068 |
2 |
TX Power Index 5GHz middle subband |
|
0x006A |
2 |
TX Power Index 5GHz low subband |
|
0x006C |
2 |
TX Power Index 5GHz low subband |
|
0x006E |
2 |
TX Power Index 5GHz high subband |
|
0x0070 |
2 |
TX Power Index 5GHz high subband |
|
Revision 8 SPROM
This revision does not inherit from older layouts
Offset |
Size |
Usage |
Notes |
0x0004 |
2 |
Subsytem product ID for PCI |
|
0x0006 |
2 |
Subsystem vendor ID for PCI |
|
0x0008 |
2 |
Product ID for PCI |
|
0x0020 |
96 |
|
48 word hardware header for PCIe rev >= 6 |
Fixed Power Indices when Power Control is disabled |
|||
0x0062 |
2 |
TX Power Index 2GHz |
|
0x0064 |
2 |
TX Power Index 2GHz |
|
0x0066 |
2 |
TX Power Index 5GHz middle subband |
|
0x0068 |
2 |
TX Power Index 5GHz middle subband |
|
0x006A |
2 |
TX Power Index 5GHz low subband |
|
0x006C |
2 |
TX Power Index 5GHz low subband |
|
0x006E |
2 |
TX Power Index 5GHz high subband |
|
0x0070 |
2 |
TX Power Index 5GHz high subband |
|
0x0080 |
2 |
SPROM Signature |
Must be 0x5372 to be a valid v8 SPROM |
0x0082 |
2 |
Board Revision |
|
0x0084 |
4 |
|
|
0x0088 |
4 |
|
|
0x008C |
6 |
MAC Address |
|
0x0092 |
2 |
Country Code |
Two characters |
0x0094 |
2 |
Regulatory Revision |
|
0x0096 |
1 |
LED 0 Behaviour |
|
0x0097 |
1 |
LED 1 Behaviour |
|
0x0098 |
1 |
LED 2 Behaviour |
|
0x0099 |
1 |
LED 3 Behaviour |
|
0x009A |
2 |
bits 15-8: LED Powersave Duty Cycle |
On Count (value is right shifted by 24) |
bits 7-0: LED Powersave Duty Cycle |
Off Count (value is right shifted by 8) |
||
0x009C |
2 |
bits 7-0: 802.11B/G Antennas Available |
Bitfield |
bits 15-8: 802.11A Antenas Available |
Bitfield |
||
0x009E |
1 |
Antenna 0 Gain |
|
0x009F |
1 |
Antenna 1 Gain |
|
0x00A0 |
1 |
Antenna 2 Gain |
|
0x00A1 |
1 |
Antenna 3 Gain |
|
0x00A2 |
2 |
TX/RX chains |
|
0x00A4 |
2 |
BXA 2G |
|
0x00A6 |
2 |
BXA 5G |
|
0x00A8 |
2 |
|
|
0x00AA |
2 |
|
|
0x00AC |
2 |
|
|
0x00AE |
2 |
antswctl2g |
Selects the RF switch arch for 2.4 GHz |
0x00B0 |
2 |
antswctl5g |
Selects the RF switch arch for 5 GHz |
Fixed Power Indices when Power Control is disabled |
|||
0x0062 |
2 |
TX Power Index 2GHz |
|
0x0064 |
2 |
TX Power Index 2GHz |
|
0x0066 |
2 |
TX Power Index 5GHz middle subband |
|
0x0068 |
2 |
TX Power Index 5GHz middle subband |
|
0x006A |
2 |
TX Power Index 5GHz low subband |
|
0x006C |
2 |
TX Power Index 5GHz low subband |
|
0x006E |
2 |
TX Power Index 5GHz high subband |
|
0x0070 |
2 |
TX Power Index 5GHz high subband |
|
Per Path Variables |
|||
0x00C0 |
- |
Path 1 Variables |
SISO PA parameters are here |
0x00E0 |
- |
Path 2 Variables |
|
0x0100 |
- |
Path 3 Variables |
|
0x0120 |
- |
Path 4 Variables |
|
Power Offsets |
|||
0x0140 |
2 |
2GHz CCK Power Offset |
|
0x0142 |
4 |
2GHz OFDM Power Offset |
|
0x0146 |
4 |
5GHz middle subband OFDM Power Offset |
|
0x014A |
4 |
5GHz low subband OFDM Power Offset |
|
0x014E |
4 |
5GHz high subband OFDM Power Offset |
|
0x0152 |
2 |
2GHz MCS Power Offset |
They may have reserved space for additional values |
0x0162 |
2 |
5GHz MCS Power Offset |
They may have reserved space for additional values |
0x0172 |
2 |
5GHz low subband MCS Power Offset |
They may have reserved space for additional values |
0x0182 |
2 |
5GHz high subband MCS Power Offset |
They may have reserved space for additional values |
0x0192 |
2 |
CCD Power Offset |
|
0x0194 |
2 |
STBC Power Offset |
|
0x0196 |
2 |
BW40 Power Offset |
|
0x0198 |
2 |
BWDUP Power Offset |
|
0x01B7 |
2 |
bits 7-0: SROM Revision |
|
Legacy names for SISO PA parameters
Offsets are given as byte offsets from the start of the Path 1 Variables
Offset |
Size |
Function |
Notes |
0x0000 |
2 |
bits 7-0: Max Power 2GHz |
|
bits 15-8: ITT 2GHz |
|
||
0x0002 |
2 |
Power Amplifier W0 PAB0 |
|
0x0004 |
2 |
Power Amplifier W0 PAB1 |
|
0x0006 |
2 |
Power Amplifier W0 PAB2 |
|
0x0008 |
2 |
bits 7-0: Max Power 5GHz |
|
bits 15-8: ITT 5GHz |
|
||
0x000A |
2 |
bits 7-0: LCHC 5GHz |
|
bits 15-8: Max Power 5GHz |
|
||
0x000C |
2 |
5GHz Power Amplifier (middle subband) W1 PAB0 |
|
0x000E |
2 |
5GHz Power Amplifier (middle subband) W1 PAB1 |
|
0x0010 |
2 |
5GHz Power Amplifier (middle subband) W1 PAB2 |
|
0x0012 |
2 |
5GHz Power Amplifier (low subband) W1 PAB0_LC |
|
0x0014 |
2 |
5GHz Power Amplifier (low subband) W1 PAB1_LC |
|
0x0016 |
2 |
5GHz Power Amplifier (low subband) W1 PAB2_LC |
|
0x0018 |
2 |
5GHz Power Amplifier (high subband) W1 PAB0_HC |
|
0x001A |
2 |
5GHz Power Amplifier (high subband) W1 PAB1_HC |
|
0x001C |
2 |
5GHz Power Amplifier (high subband) W1 PAB2_HC |
|
GPIO
If the value in the SPROM isn't 0 or 0xFFFF, the pin should be configured. GPIO pins 0 and 2 are stored in bits 7-0 of offsets 0x64 and 0x66 respectively. GPIO pins 1 and 3 are stored in bits 15-8 of offsets 0x64 and 0x66 respectively.
Calculating the CRC
The CRC value is a crc8 calculated over the first 127 bytes (that's all excluding the crc8 byte) in the SPROM (which is the crc8 byte) after byte-reversing each 16 bit word. The starting value for the crc8 is 0xFF and the final value is XOR'ed with 0xFF, the polynomial is x8+x7+x6+x4+x2+1.
Writing to the SPROM
In order to write to the SPROM, or the PCI config space SPROM Control register (pci config space 0x88) with 0x10 (WRITE ENABLE) and wait 500 msecs, then write each 16-bit word the the correct offset in the MMIO space delaying 20 msecs after each write. Then turn off the write enable bit again and again wait 500 msecs.
SPROM Contents versus Revision
If an offset is given the value is available in the srom version, if it is empty it is not available.
Label |
ssb label |
Mask |
Rev 1 |
Rev 2 |
Rev 3 |
Rev 4 |
Rev 5 |
Rev 8 |
Rev 9 |
Rev 10 |
Rev 11 |
Flags |
boardrev |
board_rev |
0x00FF (1-3) 0xFFFF (4 up) |
0x5C |
0x5C |
0x5C |
0x42 |
0x42 |
0x82 |
0x82 |
0x82 |
0x82 |
PRHEX |
boardflags |
|
0xFFFF |
0x72 |
0x72 |
0x72 |
0x44 |
0x4A |
0x84 |
0x84 |
0x84 |
0x84 |
MORE (2 up), PRHEX |
boardflags2 |
|
0xFFFF |
|
|
|
0x48 |
0x4E |
0x88 |
0x88 |
0x88 |
0x88 |
MORE, PRHEX |
boardtype |
board_type |
0xFFFF |
|
0x4 |
0x4 |
0x4 |
0x4 |
0x4 |
0x4 |
0x4 |
0x4 |
PRHEX |
boardnum |
board_num |
0xFFFF |
0x4C |
0x4C |
0x4E |
0x50 |
0x56 |
0x90 |
0x90 |
0x90 |
0x94 |
|
cc |
country_code |
0x0F00 |
0x5C |
|
|
|
|
|
|
|
|
|
regrev |
|
0xFF00 (3) 0x00FF (4 up) |
|
|
0x78 |
0x54 |
0x46 |
0x94 |
0x94 |
0x94 |
0x98 |
|
ledbh0 |
gpio0 |
0x00FF |
0x64 |
0x64 |
0x64 |
0x56 |
0x76 |
0x96 |
0x96 |
0x96 |
0x9A |
NOFFS |
ledbh1 |
gpio1 |
0xFF00 |
0x64 |
0x64 |
0x64 |
0x56 |
0x76 |
0x96 |
0x96 |
0x96 |
0x9A |
NOFFS |
ledbh2 |
gpio2 |
0x00FF |
0x66 |
0x66 |
0x66 |
0x58 |
0x78 |
0x98 |
0x98 |
0x98 |
0x9C |
NOFFS |
ledbh3 |
gpio3 |
0xFF00 |
0x66 |
0x66 |
0x66 |
0x58 |
0x78 |
0x98 |
0x98 |
0x98 |
0x9C |
NOFFS |
pa0b0 |
|
0xFFFF |
0x5E |
0x5E |
0x5E |
|
|
0xC2 |
0xC2 |
0xC2 |
|
PRHEX |
pa0b1 |
|
0xFFFF |
0x60 |
0x60 |
0x60 |
|
|
0xC4 |
0xC4 |
0xC4 |
|
PRHEX |
pa0b2 |
|
0xFFFF |
0x62 |
0x62 |
0x62 |
|
|
0xC6 |
0xC6 |
0xC6 |
|
PRHEX |
pa0itssit |
itssi_bg |
0x00FF (1-3) 0xFF00 (8 up) |
0x70 |
0x70 |
0x70 |
|
|
0xC0 |
0xC0 |
0xC0 |
|
|
pa0maxpwr |
maxpwr_bg |
0x00FF |
0x68 |
0x68 |
0x68 |
|
|
0xC0 |
0xC0 |
0xC0 |
|
|
opo |
|
0x00FF |
|
0x78 |
0x78 |
|
|
0x142 |
0x142 |
0x142 |
|
|
aa2g |
ant_available_bg |
0x3000 (1-3) 0x00FF (4 up) |
0x5C |
0x5C |
0x5C |
0x5C |
0x5C |
0x9C |
0x9C |
0x9C |
0xA0 |
|
aa5g |
ant_available_a |
0xC000 (1-3) 0xFF00 (4 up) |
0x5C |
0x5C |
0x5C |
0x5C |
0x5C |
0x9C |
0x9C |
0x9C |
0xA0 |
|
ag0 |
antenna_gain.a0 |
0x00FF |
0x74 |
0x74 |
0x74 |
0x5E |
0x5E |
0x9E |
0x9E |
0x9E |
|
|
ag1 |
antenna_gain.a1 |
0xFF00 |
0x74 |
0x74 |
0x74 |
0x5E |
0x5E |
0x9E |
0x9E |
0x9E |
|
|
ag2 |
antenna_gain.a2 |
0x00FF |
|
|
|
0x60 |
0x60 |
0xA0 |
0xA0 |
0xA0 |
|
|
ag3 |
antenna_gain.a3 |
0xFF00 |
|
|
|
0x60 |
0x60 |
0xA0 |
0xA0 |
0xA0 |
|
|
pa1b0 |
|
0xFFFF |
0x6A |
0x6A |
0x6A |
|
|
0xCC |
0xCC |
0xCC |
|
PRHEX |
pa1b1 |
|
0xFFFF |
0x6C |
0x6C |
0x6C |
|
|
0xCE |
0xCE |
0xCE |
|
PRHEX |
pa1b2 |
|
0xFFFF |
0x6E |
0x6E |
0x6E |
|
|
0xD0 |
0xD0 |
0xD0 |
|
PRHEX |
pa1lob0 |
|
0xFFFF |
|
0x3C |
0x3C |
|
|
0xD2 |
0xD2 |
0xD2 |
|
PRHEX |
pa1lob1 |
|
0xFFFF |
|
0x3E |
0x3E |
|
|
0xD4 |
0xD4 |
0xD4 |
|
PRHEX |
pa1lob2 |
|
0xFFFF |
|
0x40 |
0x40 |
|
|
0xD6 |
0xD6 |
0xD6 |
|
PRHEX |
pa1hib0 |
|
0xFFFF |
|
0x42 |
0x42 |
|
|
0xD8 |
0xD8 |
0xD8 |
|
PRHEX |
pa1hib1 |
|
0xFFFF |
|
0x44 |
0x44 |
|
|
0xDA |
0xDA |
0xDA |
|
PRHEX |
pa1hib2 |
|
0xFFFF |
|
0x46 |
0x46 |
|
|
0xDC |
0xDC |
0xDC |
|
PRHEX |
pa1itssit |
itssi_a |
0xFF00 |
0x70 |
0x70 |
0x70 |
|
|
0xC8 |
0xC8 |
0xC8 |
|
|
pa1maxpwr |
maxpwr_a |
0xFF00 (1-3) 0x00FF (8 up) |
0x68 |
0x68 |
0x68 |
|
|
0xC8 |
0xC8 |
0xC8 |
|
|
pa1lomaxpwr |
maxpwr_al |
0xFF00 |
|
0x3A |
0x3A |
|
|
0xCA |
0xCA |
0xCA |
|
|
pa1himaxpwr |
maxpwr_ah |
0x00FF |
|
0x3A |
0x3A |
|
|
0xCA |
0xCA |
0xCA |
|
|
bxa2g |
|
0x1800 |
|
|
0x50 |
|
|
0xA4 |
0xA4 |
0xA4 |
|
|
rssisav2g |
|
0x0700 |
|
|
0x50 |
|
|
0xA4 |
0xA4 |
0xA4 |
|
|
rssismc2g |
|
0x00F0 |
|
|
0x50 |
|
|
0xA4 |
0xA4 |
0xA4 |
|
|
rssismf2g |
|
0x000F |
|
|
0x50 |
|
|
0xA4 |
0xA4 |
0xA4 |
|
|
bxa5g |
|
0x1800 |
|
|
0x52 |
|
|
0xA6 |
0xA6 |
0xA6 |
|
|
rssisav5g |
|
0x0700 |
|
|
0x52 |
|
|
0xA6 |
0xA6 |
0xA6 |
|
|
rssismc5g |
|
0x00F0 |
|
|
0x52 |
|
|
0xA6 |
0xA6 |
0xA6 |
|
|
rssismf5g |
|
0x000F |
|
|
0x52 |
|
|
0xA6 |
0xA6 |
0xA6 |
|
|
tri2g |
|
0x00FF |
|
|
0x54 |
|
|
0xA8 |
0xA8 |
0xA8 |
|
|
tri5g |
|
0xFF00 |
|
|
0x54 |
|
|
0xA8 |
0xA8 |
0xA8 |
|
|
tri5gl |
|
0x00FF |
|
|
0x56 |
|
|
0xAA |
0xAA |
0xAA |
|
|
tri5gh |
|
0xFF00 |
|
|
0x56 |
|
|
0xAA |
0xAA |
0xAA |
|
|
rxpo2g |
|
0x00FF |
|
|
0x5A |
|
|
0xAC |
0xAC |
0xAC |
|
PRSIGN |
rxpo5g |
|
0xFF00 |
|
|
0x5A |
|
|
0xAC |
0xAC |
0xAC |
|
PRSIGN |
txchain |
|
0x000F |
|
|
|
0x7A |
0x7A |
0xA2 |
0xA2 |
0xA2 |
0xA8 |
NOFFS |
rxchain |
|
0x00F0 |
|
|
|
0x7A |
0x7A |
0xA2 |
0xA2 |
0xA2 |
0xA8 |
NOFFS |
antswitch |
|
0xFF00 |
|
|
|
0x7A |
0x7A |
0xA2 |
0xA2 |
0xA2 |
0xA8 |
NOFFS |
tssipos2g |
fem.ghz2.tssipos |
0x0001 |
|
|
|
|
|
0xAE |
0xAE |
0xAE |
|
|
extpagain2g |
fem.ghz2.extpa_gain |
0x0006 |
|
|
|
|
|
0xAE |
0xAE |
0xAE |
|
|
pdetrange2g |
fem.ghz2.pdet_range |
0x00F8 |
|
|
|
|
|
0xAE |
0xAE |
0xAE |
|
|
triso2g |
fem.ghz2.tr_iso |
0x0700 |
|
|
|
|
|
0xAE |
0xAE |
0xAE |
|
|
antswctl2g |
fem.ghz2.antswlut |
0xF800 |
|
|
|
|
|
0xAE |
0xAE |
0xAE |
|
|
tssipos5g |
fem.ghz5.tssipos |
0x0001 |
|
|
|
|
|
0xB0 |
0xB0 |
0xB0 |
|
|
extpagain5g |
fem.ghz5.extpa_gain |
0x0006 |
|
|
|
|
|
0xB0 |
0xB0 |
0xB0 |
|
|
pdetrange5g |
fem.ghz5.pdet_range |
0x00F8 |
|
|
|
|
|
0xB0 |
0xB0 |
0xB0 |
|
|
triso5g |
fem.ghz5.tr_iso |
0x0700 |
|
|
|
|
|
0xB0 |
0xB0 |
0xB0 |
|
|
antswctl5g |
fem.ghz5.antswlut |
0xF800 |
|
|
|
|
|
0xB0 |
0xB0 |
0xB0 |
|
|
txpid2ga0 |
txpid2g[0] |
0x00FF |
|
|
|
0x62 |
0x62 |
|
|
|
|
|
txpid2ga1 |
txpid2g[1] |
0xFF00 |
|
|
|
0x62 |
0x62 |
|
|
|
|
|
txpid2ga2 |
txpid2g[2] |
0x00FF |
|
|
|
0x64 |
0x64 |
|
|
|
|
|
txpid2ga3 |
txpid2g[3] |
0xFF00 |
|
|
|
0x64 |
0x64 |
|
|
|
|
|
txpid5ga0 |
txpid5g[0] |
0x00FF |
|
|
|
0x66 |
0x66 |
|
|
|
|
|
txpid5ga1 |
txpid5g[1] |
0xFF00 |
|
|
|
0x66 |
0x66 |
|
|
|
|
|
txpid5ga2 |
txpid5g[2] |
0x00FF |
|
|
|
0x68 |
0x68 |
|
|
|
|
|
txpid5ga3 |
txpid5g[3] |
0xFF00 |
|
|
|
0x68 |
0x68 |
|
|
|
|
|
txpid5gla0 |
txpid5gl[0] |
0x00FF |
|
|
|
0x6A |
0x6A |
|
|
|
|
|
txpid5gla1 |
txpid5gl[1] |
0xFF00 |
|
|
|
0x6A |
0x6A |
|
|
|
|
|
txpid5gla2 |
txpid5gl[2] |
0x00FF |
|
|
|
0x6C |
0x6C |
|
|
|
|
|
txpid5gla3 |
txpid5gl[3] |
0xFF00 |
|
|
|
0x6C |
0x6C |
|
|
|
|
|
txpid5gha0 |
txpid5gh[0] |
0x00FF |
|
|
|
0x6E |
0x6E |
|
|
|
|
|
txpid5gha1 |
txpid5gh[1] |
0xFF00 |
|
|
|
0x6E |
0x6E |
|
|
|
|
|
txpid5gha2 |
txpid5gh[2] |
0x00FF |
|
|
|
0x70 |
0x70 |
|
|
|
|
|
txpid5gha3 |
txpid5gh[3] |
0xFF00 |
|
|
|
0x70 |
0x70 |
|
|
|
|
|
ccode |
alpha2 |
0xFFFF |
0x76 |
0x76 |
0x76 |
0x52 |
0x44 |
0x92 |
0x92 |
0x92 |
0x96 |
CCODE |
macaddr |
il0mac |
0xFFFF |
|
|
0x4A |
0x4C |
0x52 |
0x8C |
0x8C |
0x8C |
0x90 |
ETHADDR |
il0macaddr |
il0mac |
0xFFFF |
0x48 |
0x48 |
|
|
|
|
|
|
|
ETHADDR |
et1macaddr |
et1mac |
0xFFFF |
0x54 |
0x54 |
|
|
|
|
|
|
|
ETHADDR |
leddc |
leddc_on_time leddc_off_time |
0xFFFF |
|
|
0x7C |
0x5A |
0x5A |
0x9A |
0x9A |
0x9A |
0x9E |
NOFFS, LEDDC |
tempthresh |
|
0xFF00 |
|
|
|
|
|
0xB2 |
0xB2 |
0xB2 |
0xAE |
|
tempoffset |
|
0x00FF |
|
|
|
|
|
0xB2 |
0xB2 |
0xB2 |
0xAE |
|
rawtempsense |
|
0x01FF |
|
|
|
|
|
0xB4 |
0xB4 |
0xB4 |
0xB0 |
PRHEX |
measpower |
|
0xFE00 |
|
|
|
|
|
0xB4 |
0xB4 |
0xB4 |
0xB0 |
PRHEX |
tempsense_slope |
|
0x00FF |
|
|
|
|
|
0xB6 |
0xB6 |
0xB6 |
0xB2 |
PRHEX |
tempcorrx |
|
0xFC00 |
|
|
|
|
|
0xB6 |
0xB6 |
0xB6 |
0xB2 |
PRHEX |
tempsense_option |
|
0x0300 |
|
|
|
|
|
0xB6 |
0xB6 |
0xB6 |
0xB2 |
PRHEX |
freqoffset_corr |
|
0x000F |
|
|
|
|
|
0xB8 |
0xB8 |
0xB8 |
|
PRHEX |
iqcal_swp_dis |
|
0x0010 |
|
|
|
|
|
0xB8 |
0xB8 |
0xB8 |
|
PRHEX |
hw_iqcal_en |
|
0x0020 |
|
|
|
|
|
0xB8 |
0xB8 |
0xB8 |
|
PRHEX |
elna2g |
|
0x00FF |
|
|
|
|
|
0xBA |
0xBA |
0xBA |
|
|
elna5g |
|
0xFF00 |
|
|
|
|
|
0xBA |
0xBA |
0xBA |
|
|
phycal_tempdelta |
|
0x00FF |
|
|
|
|
|
0xBC |
0xBC |
0xBC |
0xB8 |
|
temps_period |
|
0x0F00 |
|
|
|
|
|
0xBC |
0xBC |
0xBC |
0xB8 |
|
temps_hysteresis |
|
0xF000 |
|
|
|
|
|
0xBC |
0xBC |
0xBC |
0xB8 |
|
measpower1 |
|
0x007F |
|
|
|
|
|
0xBE |
0xBE |
0xBE |
0xBA |
PRHEX |
measpower2 |
|
0x3F80 |
|
|
|
|
|
0xBE |
0xBE |
0xBE |
0xBA |
PRHEX |
cck2gpo |
|
0xFFFF |
|
|
|
0x138 |
0x138 |
0x140 |
|
|
|
|
ofdm2gpo |
|
0xFFFF |
|
|
|
0x13A |
0x13A |
0x142 |
|
|
|
MORE |
ofdm5gpo |
|
0xFFFF |
|
|
|
0x13E |
0x13E |
0x146 |
|
|
|
MORE |
ofdm5glpo |
|
0xFFFF |
|
|
|
0x142 |
0x142 |
0x14A |
|
|
|
MORE |
ofdm5ghpo |
|
0xFFFF |
|
|
|
0x146 |
0x146 |
0x14E |
|
|
|
MORE |
mcs2gpo0 |
mcs2gpo[0] |
0xFFFF |
|
|
|
0x14A |
0x14A |
0x152 |
|
|
|
|
mcs2gpo1 |
mcs2gpo[1] |
0xFFFF |
|
|
|
0x14C |
0x14C |
0x154 |
|
|
|
|
mcs2gpo2 |
mcs2gpo[2] |
0xFFFF |
|
|
|
0x14E |
0x14E |
0x156 |
|
|
|
|
mcs2gpo3 |
mcs2gpo[3] |
0xFFFF |
|
|
|
0x150 |
0x150 |
0x158 |
|
|
|
|
mcs2gpo4 |
mcs2gpo[4] |
0xFFFF |
|
|
|
0x152 |
0x152 |
0x15A |
|
|
|
|
mcs2gpo5 |
mcs2gpo[5] |
0xFFFF |
|
|
|
0x154 |
0x154 |
0x15C |
|
|
|
|
mcs2gpo6 |
mcs2gpo[6] |
0xFFFF |
|
|
|
0x156 |
0x156 |
0x15E |
|
|
|
|
mcs2gpo7 |
mcs2gpo[7] |
0xFFFF |
|
|
|
0x158 |
0x158 |
0x160 |
|
|
|
|
mcs5gpo0 |
mcs5gpo[0] |
0xFFFF |
|
|
|
0x15A |
0x15A |
0x162 |
|
|
|
|
mcs5gpo1 |
mcs5gpo[1] |
0xFFFF |
|
|
|
0x15C |
0x15C |
0x164 |
|
|
|
|
mcs5gpo2 |
mcs5gpo[2] |
0xFFFF |
|
|
|
0x15E |
0x15E |
0x166 |
|
|
|
|
mcs5gpo3 |
mcs5gpo[3] |
0xFFFF |
|
|
|
0x160 |
0x160 |
0x168 |
|
|
|
|
mcs5gpo4 |
mcs5gpo[4] |
0xFFFF |
|
|
|
0x162 |
0x162 |
0x16A |
|
|
|
|
mcs5gpo5 |
mcs5gpo[5] |
0xFFFF |
|
|
|
0x164 |
0x164 |
0x16C |
|
|
|
|
mcs5gpo6 |
mcs5gpo[6] |
0xFFFF |
|
|
|
0x166 |
0x166 |
0x16E |
|
|
|
|
mcs5gpo7 |
mcs5gpo[7] |
0xFFFF |
|
|
|
0x168 |
0x168 |
0x170 |
|
|
|
|
mcs5glpo0 |
mcs5glpo[0] |
0xFFFF |
|
|
|
0x16A |
0x16A |
0x172 |
|
|
|
|
mcs5glpo1 |
mcs5glpo[1] |
0xFFFF |
|
|
|
0x16C |
0x16C |
0x174 |
|
|
|
|
mcs5glpo2 |
mcs5glpo[2] |
0xFFFF |
|
|
|
0x16E |
0x16E |
0x176 |
|
|
|
|
mcs5glpo3 |
mcs5glpo[3] |
0xFFFF |
|
|
|
0x170 |
0x170 |
0x178 |
|
|
|
|
mcs5glpo4 |
mcs5glpo[4] |
0xFFFF |
|
|
|
0x172 |
0x172 |
0x17A |
|
|
|
|
mcs5glpo5 |
mcs5glpo[5] |
0xFFFF |
|
|
|
0x174 |
0x174 |
0x17C |
|
|
|
|
mcs5glpo6 |
mcs5glpo[6] |
0xFFFF |
|
|
|
0x176 |
0x176 |
0x17E |
|
|
|
|
mcs5glpo7 |
mcs5glpo[7] |
0xFFFF |
|
|
|
0x178 |
0x178 |
0x180 |
|
|
|
|
mcs5ghpo0 |
mcs5ghpo[0] |
0xFFFF |
|
|
|
0x17A |
0x17A |
0x182 |
|
|
|
|
mcs5ghpo1 |
mcs5ghpo[1] |
0xFFFF |
|
|
|
0x17C |
0x17C |
0x184 |
|
|
|
|
mcs5ghpo2 |
mcs5ghpo[2] |
0xFFFF |
|
|
|
0x17E |
0x17E |
0x186 |
|
|
|
|
mcs5ghpo3 |
mcs5ghpo[3] |
0xFFFF |
|
|
|
0x180 |
0x180 |
0x188 |
|
|
|
|
mcs5ghpo4 |
mcs5ghpo[4] |
0xFFFF |
|
|
|
0x182 |
0x182 |
0x18A |
|
|
|
|
mcs5ghpo5 |
mcs5ghpo[5] |
0xFFFF |
|
|
|
0x184 |
0x184 |
0x18C |
|
|
|
|
mcs5ghpo6 |
mcs5ghpo[6] |
0xFFFF |
|
|
|
0x186 |
0x186 |
0x18E |
|
|
|
|
mcs5ghpo7 |
mcs5ghpo[7] |
0xFFFF |
|
|
|
0x188 |
0x188 |
0x190 |
|
|
|
|
cddpo |
|
0xFFFF |
|
|
|
0x18A |
0x18A |
0x192 |
|
|
|
|
stbcpo |
|
0xFFFF |
|
|
|
0x18C |
0x18C |
0x194 |
|
|
|
|
bw40po |
|
0xFFFF |
|
|
|
0x18E |
0x18E |
0x196 |
|
|
|
|
bwduppo |
|
0xFFFF |
|
|
|
0x190 |
0x190 |
0x198 |
|
|
|
|
cckbw202gpo |
|
0xFFFF |
|
|
|
|
|
|
0x140 |
0x140 |
0x150 |
|
cckbw20ul2gpo |
|
0xFFFF |
|
|
|
|
|
|
0x142 |
0x142 |
0x152 |
|
legofdmbw202gpo |
|
0xFFFF |
|
|
|
|
|
|
0x144 |
0x144 |
|
MORE |
legofdmbw20ul2gpo |
|
0xFFFF |
|
|
|
|
|
|
0x148 |
0x148 |
|
MORE |
legofdmbw205glpo |
|
0xFFFF |
|
|
|
|
|
|
0x14C |
0x14C |
|
MORE |
legofdmbw20ul5glpo |
|
0xFFFF |
|
|
|
|
|
|
0x150 |
0x150 |
|
MORE |
legofdmbw205gmpo |
|
0xFFFF |
|
|
|
|
|
|
0x154 |
0x154 |
|
MORE |
legofdmbw20ul5gmpo |
|
0xFFFF |
|
|
|
|
|
|
0x158 |
0x158 |
|
MORE |
legofdmbw205ghpo |
|
0xFFFF |
|
|
|
|
|
|
0x15C |
0x15C |
|
MORE |
legofdmbw20ul5ghpo |
|
0xFFFF |
|
|
|
|
|
|
0x160 |
0x160 |
|
MORE |
mcsbw202gpo |
|
0xFFFF |
|
|
|
|
|
|
0x164 |
0x164 |
0x154 |
MORE |
mcsbw20ul2gpo |
|
0xFFFF |
|
|
|
|
|
|
0x168 |
0x168 |
|
MORE |
mcsbw402gpo |
|
0xFFFF |
|
|
|
|
|
|
0x16C |
0x16C |
0x158 |
MORE |
mcsbw205glpo |
|
0xFFFF |
|
|
|
|
|
|
0x170 |
0x170 |
0x160 |
MORE |
mcsbw20ul5glpo |
|
0xFFFF |
|
|
|
|
|
|
0x174 |
0x174 |
|
MORE |
mcsbw405glpo |
|
0xFFFF |
|
|
|
|
|
|
0x178 |
0x178 |
0x164 |
MORE |
mcsbw205gmpo |
|
0xFFFF |
|
|
|
|
|
|
0x17C |
0x17C |
0x170 |
MORE |
mcsbw20ul5gmpo |
|
0xFFFF |
|
|
|
|
|
|
0x180 |
0x180 |
|
MORE |
mcsbw405gmpo |
|
0xFFFF |
|
|
|
|
|
|
0x184 |
0x184 |
0x174 |
MORE |
mcsbw205ghpo |
|
0xFFFF |
|
|
|
|
|
|
0x188 |
0x188 |
0x180 |
MORE |
mcsbw20ul5ghpo |
|
0xFFFF |
|
|
|
|
|
|
0x18C |
0x18C |
|
MORE |
mcsbw405ghpo |
|
0xFFFF |
|
|
|
|
|
|
0x190 |
0x190 |
0x184 |
MORE |
mcs32po |
|
0xFFFF |
|
|
|
|
|
|
0x194 |
0x194 |
|
|
legofdm40duppo |
|
0xFFFF |
|
|
|
|
|
|
0x196 |
0x196 |
|
|
pcieingress_war |
|
0x000F |
|
|
|
|
|
0x1A6 |
0x1A6 |
0x1A6 |
0x1B8 |
|
rxgainerr2ga0 |
rxgainerr2ga[0] |
0x003F |
|
|
|
|
|
0x19A |
0x19A |
0x19A |
|
|
rxgainerr2ga1 |
rxgainerr2ga[1] |
0x07C0 |
|
|
|
|
|
0x19A |
0x19A |
0x19A |
|
|
rxgainerr2ga2 |
rxgainerr2ga[2] |
0xF800 |
|
|
|
|
|
0x19A |
0x19A |
0x19A |
|
|
rxgainerr5gla0 |
rxgainerr5gla[0] |
0x003F |
|
|
|
|
|
0x19C |
0x19C |
0x19C |
|
|
rxgainerr5gla1 |
rxgainerr5gla[1] |
0x07C0 |
|
|
|
|
|
0x19C |
0x19C |
0x19C |
|
|
rxgainerr5gla2 |
rxgainerr5gla[2] |
0xF800 |
|
|
|
|
|
0x19C |
0x19C |
0x19C |
|
|
rxgainerr5gma0 |
rxgainerr5gma[0] |
0x003F |
|
|
|
|
|
0x19E |
0x19E |
0x19E |
|
|
rxgainerr5gma1 |
rxgainerr5gma[1] |
0x07C0 |
|
|
|
|
|
0x19E |
0x19E |
0x19E |
|
|
rxgainerr5gma2 |
rxgainerr5gma[2] |
0xF800 |
|
|
|
|
|
0x19E |
0x19E |
0x19E |
|
|
rxgainerr5gha0 |
rxgainerr5gha[0] |
0x003F |
|
|
|
|
|
0x1A0 |
0x1A0 |
0x1A0 |
|
|
rxgainerr5gha1 |
rxgainerr5gha[1] |
0x07C0 |
|
|
|
|
|
0x1A0 |
0x1A0 |
0x1A0 |
|
|
rxgainerr5gha2 |
rxgainerr5gha[2] |
0xF800 |
|
|
|
|
|
0x1A0 |
0x1A0 |
0x1A0 |
|
|
rxgainerr5gua0 |
rxgainerr5gua[0] |
0x003F |
|
|
|
|
|
0x1A2 |
0x1A2 |
0x1A2 |
|
|
rxgainerr5gua1 |
rxgainerr5gua[1] |
0x07C0 |
|
|
|
|
|
0x1A2 |
0x1A2 |
0x1A2 |
|
|
rxgainerr5gua2 |
rxgainerr5gua[2] |
0xF800 |
|
|
|
|
|
0x1A2 |
0x1A2 |
0x1A2 |
|
|
sar2g |
|
0x00FF |
|
|
|
|
|
|
0x1A8 |
0x1A8 |
0x1BA |
|
sar5g |
|
0xFF00 |
|
|
|
|
|
|
0x1A8 |
0x1A8 |
0x1BA |
|
noiselvl2ga0 |
noiselvl2ga[0] |
0x001F |
|
|
|
|
|
0x1AA |
0x1AA |
0x1AA |
0x1BC |
|
noiselvl2ga1 |
noiselvl2ga[1] |
0x03E0 |
|
|
|
|
|
0x1AA |
0x1AA |
0x1AA |
0x1BC |
|
noiselvl2ga2 |
noiselvl2ga[2] |
0x7C00 |
|
|
|
|
|
0x1AA |
0x1AA |
0x1AA |
0x1BC |
|
noiselvl5gla0 |
noiselvl5gla[0] |
0x001F |
|
|
|
|
|
0x1AC |
0x1AC |
0x1AC |
0x1BE |
|
noiselvl5gla1 |
noiselvl5gla[1] |
0x03E0 |
|
|
|
|
|
0x1AC |
0x1AC |
0x1AC |
0x1BE |
|
noiselvl5gla2 |
noiselvl5gla[2] |
0x7C00 |
|
|
|
|
|
0x1AC |
0x1AC |
0x1AC |
0x1BE |
|
noiselvl5gma0 |
noiselvl5gma[0] |
0x001F |
|
|
|
|
|
0x1AE |
0x1AE |
0x1AE |
0x1C0 |
|
noiselvl5gma1 |
noiselvl5gma[1] |
0x03E0 |
|
|
|
|
|
0x1AE |
0x1AE |
0x1AE |
0x1C0 |
|
noiselvl5gma2 |
noiselvl5gma[2] |
0x7C00 |
|
|
|
|
|
0x1AE |
0x1AE |
0x1AE |
0x1C0 |
|
noiselvl5gha0 |
noiselvl5gha[0] |
0x001F |
|
|
|
|
|
0x1B0 |
0x1B0 |
0x1B0 |
0x1C2 |
|
noiselvl5gha1 |
noiselvl5gha[1] |
0x03E0 |
|
|
|
|
|
0x1B0 |
0x1B0 |
0x1B0 |
0x1C2 |
|
noiselvl5gha2 |
noiselvl5gha[2] |
0x7C00 |
|
|
|
|
|
0x1B0 |
0x1B0 |
0x1B0 |
0x1C2 |
|
noiselvl5gua0 |
noiselvl5gua[0] |
0x001F |
|
|
|
|
|
0x1B2 |
0x1B2 |
0x1B2 |
0x1C4 |
|
noiselvl5gua1 |
noiselvl5gua[1] |
0x03E0 |
|
|
|
|
|
0x1B2 |
0x1B2 |
0x1B2 |
0x1C4 |
|
noiselvl5gua2 |
noiselvl5gua[2] |
0x7C00 |
|
|
|
|
|
0x1B2 |
0x1B2 |
0x1B2 |
0x1C4 |
|
subband5gver |
|
0x0007 (8-10) 0xFFFF (11 up) |
|
|
|
|
|
0x1A4 |
0x1A4 |
0x1A4 |
0xD6 |
PRHEX (11 up) |
cckPwrOffset |
|
0xFFFF |
|
|
|
|
|
|
|
0x1B4 |
|
|
swctrlmap_2g |
|
0xFFFF |
|
|
|
|
|
|
|
0x1B8 |
|
MORE, PRHEX, ARRAY |
boardflags3 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x8A |
MORE, PRHEX |
agbg0 |
|
0x00FF |
|
|
|
|
|
|
|
|
0xA2 |
|
agbg1 |
|
0xFF00 |
|
|
|
|
|
|
|
|
0xA2 |
|
agbg2 |
|
0x00FF |
|
|
|
|
|
|
|
|
0xA4 |
|
aga0 |
|
0xFF00 |
|
|
|
|
|
|
|
|
0xA4 |
|
aga1 |
|
0x00FF |
|
|
|
|
|
|
|
|
0xA6 |
|
aga2 |
|
0xFF00 |
|
|
|
|
|
|
|
|
0xA6 |
|
tssiposslope2g |
|
0x0001 |
|
|
|
|
|
|
|
|
0xAA |
|
epagain2g |
|
0x000E |
|
|
|
|
|
|
|
|
0xAA |
|
pdgain2g |
|
0x01F0 |
|
|
|
|
|
|
|
|
0xAA |
|
tworangetssi2g |
|
0x0200 |
|
|
|
|
|
|
|
|
0xAA |
|
papdcap2g |
|
0x0400 |
|
|
|
|
|
|
|
|
0xAA |
|
femctrl |
|
0xF800 |
|
|
|
|
|
|
|
|
0xAA |
|
tssiposslope5g |
|
0x0001 |
|
|
|
|
|
|
|
|
0xAC |
|
epagain5g |
|
0x000E |
|
|
|
|
|
|
|
|
0xAC |
|
pdgain5g |
|
0x01F0 |
|
|
|
|
|
|
|
|
0xAC |
|
tworangetssi5g |
|
0x0200 |
|
|
|
|
|
|
|
|
0xAC |
|
papdcap5g |
|
0x0400 |
|
|
|
|
|
|
|
|
0xAC |
|
gainctrlsph |
|
0xF800 |
|
|
|
|
|
|
|
|
0xAC |
|
pdoffset40ma0 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0xCA |
|
pdoffset40ma1 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0xCC |
|
pdoffset40ma2 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0xCE |
|
pdoffset80ma0 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0xD0 |
|
pdoffset80ma1 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0xD2 |
|
pdoffset80ma2 |
|
0xFFFF |
|
|
|
|
|
|
|
|
0xD4 |
|
dot11agofdmhrbw202gpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x15C |
|
ofdmlrbw202gpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x15E |
|
mcsbw805glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x168 |
MORE |
mcsbw1605glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x16C |
MORE |
mcsbw805gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x178 |
MORE |
mcsbw1605gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x17C |
MORE |
mcsbw805ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x188 |
MORE |
mcsbw1605ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x18C |
MORE |
mcslr5glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x190 |
|
mcslr5gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x192 |
|
mcslr5ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x194 |
|
sb20in40hrrpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x196 |
|
sb20in80and160hr5glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x198 |
|
sb40and80hr5glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x19A |
|
sb20in80and160hr5gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x19C |
|
sb40and80hr5gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x19E |
|
sb20in80and160hr5ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1A0 |
|
sb40and80hr5ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1A2 |
|
sb20in40lrpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1A4 |
|
sb20in80and160lr5glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1A6 |
|
sb40and80lr5glpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1A8 |
|
sb20in80and160lr5gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1AA |
|
sb40and80lr5gmpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1AC |
|
sb20in80and160lr5ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1AE |
|
sb40and80lr5ghpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1B0 |
|
dot11agduphrpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1B2 |
|
dot11agduplrpo |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1B4 |
|
rxgainerr2g |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1C6 |
PRHEX |
rxgainerr5g |
|
0xFFFF |
|
|
|
|
|
|
|
|
0x1C8 |
PRHEX, ARRAY |
Per Path Variables
Label |
ssb label |
Mask |
Rev 4 |
Rev 5 |
Rev 8 |
Rev 9 |
Rev 10 |
Rev 11 |
Flags |
maxp2ga |
maxpwr_2g |
0x00ff |
0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
|
itt2ga |
itssi_2g |
0xff00 |
0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
|
|
itt5ga |
itssi_5g |
0xff00 |
0xa |
0xa |
0x8 |
0x8 |
0x8 |
|
|
pa2gw0a |
pa_2g[0] |
0xffff |
0x2 |
0x2 |
0x2 |
0x2 |
0x2 |
|
PRHEX |
pa2gw1a |
pa_2g[1] |
0xffff |
0x4 |
0x4 |
0x4 |
0x4 |
0x4 |
|
PRHEX |
pa2gw2a |
pa_2g[2] |
0xffff |
0x6 |
0x6 |
0x6 |
0x6 |
0x6 |
|
PRHEX |
pa2gw3a |
pa_2g[3] |
0xffff |
0x8 |
0x8 |
|
|
|
|
PRHEX |
maxp5ga |
maxpwr_5g |
0x00ff |
0xa |
0xa |
0x8 |
0x8 |
0x8 |
0xc |
ARRAY (11 up) |
maxp5gha |
maxpwr_5gh |
0x00ff |
0xc |
0xc |
0xa |
0xa |
0xa |
|
|
maxp5gla |
maxpwr_5gl |
0xff00 |
0xc |
0xc |
0xa |
0xa |
0xa |
|
|
pa5gw0a |
pa_5g[0] |
0xffff |
0xe |
0xe |
0xc |
0xc |
0xc |
|
PRHEX |
pa5gw1a |
pa_5g[1] |
0xffff |
0x10 |
0x10 |
0xe |
0xe |
0xe |
|
PRHEX |
pa5gw2a |
pa_5g[2] |
0xffff |
0x12 |
0x12 |
0x10 |
0x10 |
0x10 |
|
PRHEX |
pa5gw3a |
pa_5g[3] |
0xffff |
0x14 |
0x14 |
|
|
|
|
PRHEX |
pa5glw0a |
pa_5gl[0] |
0xffff |
0x16 |
0x16 |
0x12 |
0x12 |
0x12 |
|
PRHEX |
pa5glw1a |
pa_5gl[1] |
0xffff |
0x18 |
0x18 |
0x14 |
0x14 |
0x14 |
|
PRHEX |
pa5glw2a |
pa_5gl[2] |
0xffff |
0x1a |
0x1a |
0x16 |
0x16 |
0x16 |
|
PRHEX |
pa5glw3a |
pa_5gl[3] |
0xffff |
0x1c |
0x1c |
|
|
|
|
PRHEX |
pa5ghw0a |
pa_5gh[0] |
0xffff |
0x1e |
0x1e |
0x18 |
0x18 |
0x18 |
|
PRHEX |
pa5ghw1a |
pa_5gh[1] |
0xffff |
0x20 |
0x20 |
0x1a |
0x1a |
0x1a |
|
PRHEX |
pa5ghw2a |
pa_5gh[2] |
0xffff |
0x22 |
0x22 |
0x1c |
0x1c |
0x1c |
|
PRHEX |
pa5ghw3a |
pa_5gh[3] |
0xffff |
0x24 |
0x24 |
|
|
|
|
PRHEX |
pa2ga |
|
0xffff |
|
|
|
|
|
0x2 |
PRHEX, ARRAY |
rxgains5gmelnagaina |
|
0x0007 |
|
|
|
|
|
0x8 |
|
rxgains5gmtrisoa |
|
0x0078 |
|
|
|
|
|
0x8 |
|
rxgains5gmtrelnabypa |
|
0x0080 |
|
|
|
|
|
0x8 |
|
rxgains5ghelnagaina |
|
0x0700 |
|
|
|
|
|
0x8 |
|
rxgains5ghtrisoa |
|
0x7800 |
|
|
|
|
|
0x8 |
|
rxgains5ghtrelnabypa |
|
0x8000 |
|
|
|
|
|
0x8 |
|
rxgains2gelnagaina |
|
0x0007 |
|
|
|
|
|
0xa |
|
rxgains2gtrisoa |
|
0x0078 |
|
|
|
|
|
0xa |
|
rxgains2gtrelnabypa |
|
0x0080 |
|
|
|
|
|
0xa |
|
rxgains5gelnagaina |
|
0x0700 |
|
|
|
|
|
0xa |
|
rxgains5gtrisoa |
|
0x7800 |
|
|
|
|
|
0xa |
|
rxgains5gtrelnabypa |
|
0x8000 |
|
|
|
|
|
0xa |
|
pa5ga |
|
0xffff |
|
|
|
|
|
0x10 |
PRHEX, ARRAY |
Path Offsets
|
Rev 4-5 |
Rev 8-10 |
Rev 11 |
Path1 |
0x80 |
0xC0 |
0xD8 |
Path2 |
0xAE |
0xE0 |
0x100 |
Path3 |
0xDC |
0x100 |
0x128 |
Path4 |
0x10A |
0x120 |
|