bcm-v4

[Specification] 

LP PHY Rev 2 Baseband Init

  1. Write 0x50 to PHY Register 0x439

  2. Write 0x8800 to PHY Register 0x43A

  3. Write 0 to the following PHY Registers

    • 0x43B
    • 0x43C
    • 0x44C
    • 0x4B0
    • 0x4F9
    • 0x44E

  4. Set bit 0x10 in PHY Register 0x470

  5. MaskSet PHY Register 0x417 with mask 0xFF00 and set 0xB4

  6. MaskSet PHY Register 0x41C with mask 0xF8FF and set 0x200

  7. MaskSet PHY Register 0x41C with mask 0xFF00 and set 0x7F

  8. MaskSet PHY Register 0x427 with mask 0xFF0F and set 0x40

  9. MaskSet PHY Register 0x41E with mask 0xFF00 and set 0x2

  10. Clear bit 0x4000 in PHY Register 0x410

  11. Clear bit 0x2000 in PHY Register 0x410

  12. Set bit 0x1 in PHY Register 0x50A

  13. MaskSet PHY Register 0x418 with mask 0xFFF0 and set with 3

  14. If Board revision >= 0x18

    1. MaskSet PHY Register 0x50A with mask 0xFF01 and set 0x14

    2. Write the LP table with ID 17, offset 65, length 1, width 8, PHY width of 32 and data 0xEC

  15. Otherwise

    1. MaskSet PHY Register 0x50A with mask 0xFF01 and set 0x10

  16. MaskSet PHY Register 0x4DF with mask 0xFF00 and set 0xF4

  17. MaskSet PHY Register 0x4DF with mask 0x00FF and set 0xF100

  18. Write 0x48 to PHY Register 0x41F

  19. MaskSet PHY Register 0x423 with mask 0xFF00 and set 0x46

  20. MaskSet PHY Register 0x4E4 with mask 0xFF00 and set 0x10

  21. MaskSet PHY Register 0x429 with mask 0xFFF0 and set 0x9

  22. Clear bits 0xF in PHY Register 0x427

  23. MaskSet PHY Register 0x425 with mask 0x00FF and set 0x5500

  24. MaskSet PHY Register 0x420 with mask 0xFC1F and set 0xA0

  25. MaskSet PHY Register 0x427 with mask 0xE0FF and set 0x300

  26. MaskSet PHY Register 0x423 with mask 0x00FF and set 0x2A00

  27. MaskSet PHY Register 0x424 with mask 0x00FF and set 0x1E00

  28. MaskSet PHY Register 0x425 with mask 0xFF00 and set 0xD

  29. MaskSet PHY Register 0x4FE with mask 0xFFE0 and set 0x1F

  30. MaskSet PHY Register 0x4FF with mask 0xFFE0 and set 0xC

  31. MaskSet PHY Register 0x500 with mask 0xFF00 and set 0x19

  32. MaskSet PHY Register 0x4FF with mask 0x03FF and set 0x3C00

  33. MaskSet PHY Register 0x4FE with mask 0xFC1F and set 0x3E0

  34. MaskSet PHY Register 0x4FF with mask 0xFFE0 and set 0xC

  35. MaskSet PHY Register 0x500 with mask 0x00FF and set 0x1900

  36. MaskSet PHY Register 0x420 with mask 0x83FF and set 0x5800

  37. MaskSet PHY Register 0x420 with mask 0xFFE0 and set 0x12

  38. MaskSet PHY Register 0x426 with mask 0x0FFF and set 0x9000

  39. If operating in 2 GHz band

    1. Set bit 0x40 in PHY Register 0x410

    2. MaskSet PHY Register 0x410 with mask 0xF0FF and set 0xB00

    3. MaskSet PHY Register 0x30 with mask 0xFFF8 and set 0x6

    4. MaskSet PHY Register 0x416 with mask 0x00FF and set 0x9D00

    5. MaskSet PHY Register 0x416 with mask 0xFF00 and set 0xA1

  40. Otherwise

    1. Clear bit 0x40 in PHY Register 0x410

  41. MaskSet PHY Register 0x432 with mask 0xFF00 and set 0xB3

  42. MaskSet PHY Register 0x432 with mask 0x00FF and set 0xAD00

  43. If operating in 2 GHz band

    1. MaskSet PHY Register 0x434 with mask 0xFF00 and set with lpphy_rx_power_offset_2g

  44. Otherwise

    1. MaskSet PHY Register 0x434 with mask 0xFF00 and set with lpphy_rx_power_offset_5g

  45. Set bits 0x44 in PHY Register 0x44A

  46. Write 0x80 to PHY Register 0x44A

  47. Write 0xA954 to PHY Register 0x43D

  48. If operating in 2 GHz band

    1. Set tmp to lpphy_rssi_vf_2g | (lpphy_rssi_vc_2g << 4) | 0x2000 | (lpphy_rssi_gs_2g << 10)

  49. Otherwise

    1. Set tmp to lpphy_rssi_vf_5g | (lpphy_rssi_vc_5g << 4) | 0x2000 | (lpphy_rssi_gs_5g << 10)

  50. Write tmp to PHY Register 0x43E

  51. If the chip ID is 0x4325 and the chip revision >= 3

    1. Define u8 tdata and initialize to 11, 17, 20, 29, -5, 4, 10, 13
    2. Write an LP PHY table with ID 17, length 8, offset 0, width 8, PHY width 32, and data tdata

    3. Set bits 0xFF in PHY Register 0x434

    4. MaskSet PHY Register 0x425 with mask 0x00FF and set with 0x5100

    5. MaskSet PHY Register 0x416 with mask 0x00FF and set with 0xA300

  52. Set lpphy_cck_papd_disabled to 1

  53. Set bit 0x4000 in MAC control
  54. Do a dummy read of MAC control
  55. Delay 1 usec
  56. If the chip ID is 0x4325 AND bit 0x1000 is set in boardflags AND this is a 2 GHz channel
    1. If the boardtype is 0x04C6
      1. Set bit 0x8 in PHY Register 0x4DE

      2. MaskSet PHY Register 0x4E1 with mask 0x80FF and set with 0x0C00

      3. MaskSet PHY Register 0x4E1 with mask 0xFF80 and set with 0x000F

      4. Write LP PHY Table with ID 17, offset 66, length 2, width 8, PHY width 32, and data -15, 12
      5. Write LP PHY Table with ID 17, offset 0, length 4, width 8, PHY width 32, and data 5, 9, 14, 21
      6. Write LP PHY Table with ID 17, offset 4, length 4, width 8, PHY width 32, and data 0, 10, 15, 20

      7. MaskSet PHY Register 0x4E4 with mask 0xFF00 and set with 0x30

      8. MaskSet PHY Register 0x50A with mask 0xFF01 and set with 0x14

      9. Read LP PHY Table with ID 17, offset 64, length 1, width 8, PHY width 32, and data s8 buffer

      10. If buffer > 63

        1. Reduce buffer by 128
      11. Read PHY Register 0x50A, mask with 0xFE, right shift the result by 1, and save in tmp32
      12. Set tmp32 to buffer - 3 * tmp32
      13. Define s8 tab1 with data buffer, tmp32
      14. Write LP PHY Table with ID 17, offset 64, length 2, width 8, PHY width 32, and data tab1

      15. MaskSet PHY Register 0x417 with mask 0xFF00 and set with 0x00A0

      16. MaskSet PHY Register 0x417 with mask 0x00FF and set with 0x5500

      17. MaskSet PHY Register 0x418 with mask 0xFFF0 and set with 0x0002

      18. MaskSet PHY Register 0x418 with mask 0xF0FF and set with 0x0300

      19. MaskSet PHY Register 0x41B with mask 0xF03F and set with 0x0300

      20. MaskSet PHY Register 0x50A with mask 0xFFFE and set with 0x0001

      21. MaskSet PHY Register 0x434 with mask 0xFF00 and set with 0x00FF

      22. MaskSet PHY Register 0x425 with mask 0xFF00 and set with 0x000E

      23. MaskSet PHY Register 0x424 with mask 0x00FF and set with 0x2300

      24. MaskSet PHY Register 0x420 with mask 0xFC1F and set with 0x0140

      25. MaskSet PHY Register 0x427 with mask 0xE0FF and set with 0x0300

      26. MaskSet PHY Register 0x420 with mask 0xC3FF and set with 0x5800

      27. MaskSet PHY Register 0x420 with mask 0xFFC3 and set with 0x0012

      28. MaskSet PHY Register 0x423 with mask 0xFF00 and set with 0x0049

      29. MaskSet PHY Register 0x429 with mask 0xFFF0 and set with 0x0009

      30. MaskSet PHY Register 0x427 with mask 0xFFF0 and set with 0x0000

      31. MaskSet PHY Register 0x430 with mask 0xF03F and set with 0x0380

      32. MaskSet PHY Register 0x421 with mask 0xFF00 and set with 0x0008

      33. MaskSet PHY Register 0x421 with mask 0xE0FF and set with 0x0800

      34. Read PHY Register 0x420, mask with 0x03E0, right shift result by 5, and save as tmp16

      35. MaskSet PHY Register 0x4FE with mask 0xFFE0 and set with tmp16

      36. MaskSet PHY Register 0x4FE with mask 0xFC1F and set with tmp16 << 5

      37. Read PHY Register 0x427, mask with 0x1F00, right shift result by 8, and save as tmp16

      38. MaskSet PHY Register 0x4FF with mask 0xE1FF and set with tmp16

      39. MaskSet PHY Register 0x4FF with mask 0xFC1F and set with tmp16 << 5

      40. Read PHY Register 0x425, mask with 0x00FF, and save as tmp16

      41. MaskSet PHY Register 0x500 with mask 0xFF00 and set with tmp16

      42. MaskSet PHY Register 0x500 with mask 0x00FF and set with tmp16 << 8

    2. Otherwise
      1. Set bit 8 in PHY Regiseter 0x4DE

      2. MaskSet PHY Register 0x4E1 with mask 0x80FF and set with 0x0A00

      3. MaskSet PHY Register 0x4E1 with mask 0xFF80 and set with 0x00F5

      4. Write LP PHY table with ID 17, offset 66, length 2, width 8, PHY width 32, and data -11, 10
      5. Write LP PHY table with ID 17, offset 0, length 8, width 8, PHY width 32, and data 8, 13, 21, 27, -5, 4, 8, 13

      6. MaskSet PHY Register 0x50A with mask 0xFF01 and set with 0x0010

      7. Write LP PHY table with ID 17, offset 64, length 2, width 8, PHY width 32, and data 7, -17

      8. MaskSet PHY Register 0x4E4 with mask 0xFF00 and set with 0x0030

      9. MaskSet PHY Register 0x417 with mask 0xFF00 and set with 0x00A0

      10. MaskSet PHY Register 0x417 with mask 0x00FF and set with 0x5500

      11. MaskSet PHY Register 0x418 with mask 0xFFF0 and set with 0x0002

      12. MaskSet PHY Register 0x418 with mask 0xF0FF and set with 0x0200

      13. MaskSet PHY Register 0x423 with mask 0xFF00 and set with 0x0049

    3. Set bits 0x44 in PHY Register 0x44A a, Write 0x80 to PHY Register 0x44A

  57. Call LP PHY Rev2 TX Dig Filter Set with a pointer to LP PHY Rev2 TX Dig Filter Coef OFDM table as argument

  58. Call LP PHY Rev2 TX Dig Filter ucode Set with 0 and a pointer to LP PHY Rev2 TX Dig Filter Coef OFDM table as arguments

  59. If boardflags & 0x01000000 is not zero

    1. Call LP PHY Rev2 TX Dig Filter ucode Set with 1 and a pointer to LP PHY Rev2 TX Dig Filter Coef CCK EVM as arguments

  60. Otherwise

    1. Call LP PHY Rev2 TX Dig Filter ucode Set with 1 and a pointer to LP PHY Rev2 TX Dig Filter Coef CCK SM as arguments

LP PHY Rev2 TX Dig Filter Coef OFDM

0xec4d

0xe831

0xe330

0x3018

0x0018

0xfa20

0x0020

0xc340

0x0040

LP PHY Rev2 TX Dig Filter Coef CCK SM

0xd75a

0xec2f

0xee30

0xaa54

0x0054

0xf01a

0x001a

0x1610

0x0010

LP PHY Rev2 TX Dig Filter Coef CCK EVM

0xd758

0xec2f

0xee30

0xbd5e

0x005e

0xfb1a

0x001a

0x0f08

0x0008

Exported/Archived from the wiki to HTML on 2016-10-27