bcm-v4

[Specification

This was previously called 2050 Radio Core Calibration. It's only called during PHY Init.

Init Routine

  1. Accumulator 1 and 2 are both set to 0
  2. Backup Radio Registers 0x43, 0x51, 0x52

  3. Backup PHY Registers 0x15, 0x5A, 0x59, 0x58

  4. If this is a B PHY
    1. Backup PHY Register offset 0x30

    2. Backup Core Register 0x3EC

    3. Write 0xFF to PHY Register 0x30

    4. Write 0x3F3F to Core Register 0x3EC

  5. If this is not a B PHY and (Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater)

    1. Back up PHY Registers 0x811, 0x812, 0x814, 0x815, 0x429, 0x802

    2. OR PHY Register 0x814 with 3

    3. AND PHY Register 0x815 with 0xFFFC

    4. AND PHY Register 0x429 with 0x7FFF

    5. AND PHY Register 0x802 with 0xFFFC

    6. If Loopback Gain is enabled

      1. Backup PHY Register 0x80F

      2. Backup PHY Register 0x810

      3. If the PHY Revision is 3 or greater
        1. Write 0xC020 to PHY Register 0x80F

      4. Otherwise
        1. Write 0x8020 to PHY Register 0x80F

      5. Write 0 to PHY Register 0x810

    7. Write the L = 0, P = 1, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

    8. Write the PHY Register 0x811 value from the table below to PHY Register 0x811

  6. OR Core Register 0x3E2 with 0x8000

  7. Backup PHY Register 0x35

  8. AND PHY Register 0x35 with 0xFF7F

  9. Backup Core Register 0x3E6, 0x3F4

  10. If the Analog Core Revision is 0

    1. Write 0x122 to Core Register 0x3E6

  11. Otherwise
    1. If the Analog Core Revision is 2 or greater

      1. MaskSet PHY Register 0x3 with mask 0xFFBF and set with 0x40

    2. OR Core Register 0x3F4 with 0x2000

  12. Find the Radio Core Calibration value using the RCC Table

  13. If this is a B PHY
    1. Write 0x26 into Radio Register 0x78

  14. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

    1. Write the L = 0, P = 1, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

  15. Write 0xBFAF to PHY Register 0x15

  16. Write 0x1403 to PHY Register 0x2B

  17. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

    1. Write the L = 0, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

  18. Write 0xBFA0 to PHY Register 0x15

  19. OR Radio Register 0x51 with 0x4

  20. If the Radio Revision is 8
    1. Write 0x1F into Radio Register 0x43

  21. Otherwise
    1. Write 0 to Radio Register 0x52

    2. MaskSet Radio Register 0x43 with mask 0xFFF0 and set with 0x9

  22. Write 0 to PHY Register 0x58

  23. Loop 16 times
    1. Write 0x480 to PHY Register 0x5A

    2. Write 0xC810 to PHY Register 0x59

    3. Write 0xD to PHY Register 0x58

    4. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

      1. Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

    5. Write 0xAFB0 to PHY Register 0x15

    6. Delay 10 uSec
    7. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

      1. Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

    8. Write 0xEFB0 to PHY Register 0x15

    9. Delay 10 uSec
    10. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

      1. Write the L = 1, P = 0, D = 0 PHY Register 0x812 value from the table below to PHY Register 0x812

    11. Write 0xFFF0 to PHY Register 0x15

    12. Delay 20 uSec
    13. Read the value of PHY Register 0x2D and add it to Accumulator 1

    14. Write 0 to PHY Register 0x58

    15. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

      1. Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

    16. Write 0xAFB0 to PHY Register 0x15

  24. Delay 10 uSec
  25. Write 0 to PHY Register 0x58

  26. Add 1 to the value of Accumulator 1 then right shift by 9.
  27. Loop 16 times from 0 to 15
    1. Take the bit-reversed loop index (a 4 bit value) and left shift it by 1
    2. OR the result with 0x20
    3. Write this value to Radio Register 0x78

    4. Save the value of Radio Register 0x78

    5. Delay 10 usec
    6. Loop 16 times
      1. Write 0xD80 to PHY Register 0x5A

      2. Write 0xC810 to PHY Register 0x59

      3. Write 0xD to PHY Register 0x58

      4. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

        1. Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

      5. Write 0xAFB0 to PHY Register 0x15

      6. Delay 10 usec
      7. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

        1. Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

      8. Write 0xEFB0 to PHY Register 0x15

      9. Delay 10 usec
      10. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

        1. Write the L = 1, P = 0, D = 0 PHY Register 0x812 value from the table below to PHY Register 0x812

      11. Write 0xFFF0 to PHY Register 0x15

      12. Delay 10 usec
      13. Read the value of PHY Register 0x2D and add it to Accumulator 2

      14. Write 0 to PHY Register 0x58

      15. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

        1. Write the L = 1, P = 0, D = 1 PHY Register 0x812 value from the table below to PHY Register 0x812

      16. Write 0xAFB0 to PHY Register 0x15

    7. Increment Accumulator 2 then right shift by 8
    8. If Accumulator 1 is less than Accumulator 2, break from the loop
  28. Restore the original value of PHY Register 0x15

  29. Restore the original values of Radio Registers 0x51, 0x52, 0x43

  30. Restore the original values of PHY Registers 0x5A, 0x59, 0x58

  31. Restore the original value of Core Register 0x3E6

  32. If the Analog Core Revision is not 0

    1. Restore the original value of Core Register 0x3F4

  33. Restore the original value of PHY Register 0x35

  34. Perform the Synthetic PU Workaround (channel selection)

  35. If this is a B PHY
    1. Restore the original value of PHY Register 0x30

    2. Restore the original value of Core Register 0x3EC

  36. If this isn't a B PHY and Core Flags has the G Mode Enable flag (0x20000000) set

    1. AND Core Register 0x3E2 with 0x7FFF

    2. Restore the value of PHY Registers 0x811, 0x812, 0x814, 0x815, 0x429 and 0x802

    3. If Loopback Gain is enabled
      1. Restore PHY Registers 0x80F and 0x810

  37. If we went through all of the loops in Loop 2
    1. Return the saved value of Radio Register 0x78

  38. Otherwise
    1. Return the value from the RCC Table

Value Table

All values are 0 if Core Flags doesn't have the G Mode Enable flag (0x20000000) set and the PHY Revision isn't 2 or greater

Loopback Gain Disabled

PHY Revision < 7 or Board Flags BFL_EXTLNA isn't set

GPHY Register 0x811 Value

0x1B3

GPHY Register 0x812 Value

L

P

D

Value

0

1

1

0x0FB2

0

0

1

0x00B2

1

0

1

0x30B2

1

0

0

0x30B3

Otherwise

GPHY Register 0x811 Value

0x9B3

GPHY Register 0x812 Value

L

P

D

Value

0

1

1

0x8FB2

0

0

1

0x80B2

1

0

1

0x20B2

1

0

0

0x20B3

Otherwise

  1. If the Radio Revision is 8
    1. Take the Maximum Loopback Gain (in half dB) and add 0x3E to the value
  2. Otherwise
    1. Take the Maximum Loopback Gain (in half dB) and add 0x26 to the value
  3. Using the correct value from the table below, subtract it from the result
  4. Loop up to 16 times, from 0 to 15
    1. Subtract 6 times the loop position from the value found above
    2. If this result is less than 6
      1. Break the loop
  5. Use the final loop position value and the External LNA value below to find the table values

External LNA Control Table

Adjusted Maximum Loopback Gain Value

External LNA Control Value

Value to Subtract

>= 0x46

0x3000

0x46

0x45 >= x >= 0x3A

0x1000

0x3A

0x39 >= x >= 0x2E

0x2000

0x2E

Otherwise

0x0000

0x10

PHY Revision < 7 or Board Flags BFL_EXTLNA isn't set

GPHY Register 0x811 Value

0x1B3

  1. OR the loop position value left shifted by 8 with the External LNA Control Value
  2. OR this value with the table values below which are marked with Yes

GPHY Register 0x812 Value

L

P

D

Value

OR'd with the value above

0

1

1

0x0F92

No

0

0

1

0x0092

Yes

1

0

1

0x0092

Yes

1

0

0

0x0093

Yes

Otherwise

GPHY Register 0x811 Value

0x9B3

  1. If the value from the External LNA Control Value table isn't 0
    1. OR the the External LNA Control value with 0x8000
  2. OR the loop position value left shifted by 8 with the External LNA Control Value
  3. OR this value with the table values below which are marked with Yes

GPHY Register 0x812 Value

L

P

D

Value

OR'd with the value above

0

1

1

0x8F92

No

0

0

1

0x8092

Yes

1

0

1

0x2092

Yes

1

0

0

0x2093

Yes


Exported/Archived from the wiki to HTML on 2016-10-27