N PHY channel switch

• if 40 MHz channel, set bit 0x10 in register 0xa0 for upper, clear for lower sideband

• for rev >= 3

  • set bit 0x4 in radio register 0x8 for 5ghz, clear otherwise
  • set 2056 radio channel
  • setup channel (see below)

• rev < 3

  • set bits 0x70 in radio register 0x11 to 2 for 5ghz, 5 for 2.4 ghz
  • set 2055 radio channel
  • setup channel (see below)

setup channel

• read phy register 0x09
• if switching to 5ghz and bit 0x1 in 0x09 is unset
  • save and then set bit 0x4 in MAC register 0x492
  • set bits 0xc000 in PHY reg 0xc01
  • restore MAC register 0x492
  • set bit 0x1 in phy register 0x09
• if switching to 2.4ghz and the bit 0x1 in 0x09 is set
  • clear bit 0x1 in phy reg 0x09
  • save and then set bit 0x4 in MAC register 0x492
  • clear bits 0xc000 in PHY reg 0xc01
  • restore MAC register 0x492
• write the table values for phy regs 0x1ce, 0x1cf, 0x1d0, 0x1d1, 0x1d2, 0x1d3 (listed on the radio tables)
• update the shm channel value (radio code or'ed with: 40 mhz: 0x200 / 5ghz: 0x100)
• channel 14:
  • classifier 0x2 off
  • set bit 0x800 in phy reg 0xc0a
• otherwise:
  • classifier 0x2 on
  • clear bits 0x840 in phy reg 0xc0a
• fix TX power if tx power control is off

• adjust LNA gain tables for PHY rev < 3

• do TX LPF bandwidth adjustment

• if spur avoidance is wanted (default auto which means channels 5-8, 13, 14 for 20mhz; channels 38, 102, 118 if A Band spur workaround enabled (boardflags) for 40 mhz) and phy revision is >= 3

  • turn off PHY PLL
  • do ssb PMU spuravoidance with wanted value
  • turn on PHY PLL
  • do PHY PLL reset
  • set bit 0x8000 in phy register 0x1 depending on spuravoidance (on if on, off if off)
  • reset CCA
• write 0x3830 to phy reg 0x17e
• do spur avoidance workaround