N PHY Superswitch init (bool init)

1. If PHY Revision >= 3

   1. If init is 0
      1. Return

   2. If srom_fem2g.antswctrllut is zero

      1. Write an N PHY Table with ID 9, length 1, offset 2, width 16, and data 0x211
      2. Write an N PHY Table with ID 9, length 1, offset 3, width 16, and data 0x222
      3. Write an N PHY Table with ID 9, length 1, offset 8, width 16, and data 0x144
      4. Write an N PHY Table with ID 9, length 1, offset 12, width 16, and data 0x188
2. Otherwise
   1. Write 0x0000 to PHY Register 0xC8
   2. Write 0x0000 to PHY Register 0xC9
   3. Set bits 0x0000FC00 in SSB PCICORE_GPIO_CTL
   4. Clear bits 0x0000C000 in MMIO MAC CONTROL register
   5. Set bits 0xFC00 in the MMIO GPIO MASK register
   6. Clear bits 0xFC00 in the MMIO GPIO CONTROL register
   7. If init is true
      1. Write 0x02D8 to PHY Register 0xF8
      2. Write 0x0301 to PHY Register 0xF9
      3. Write 0x02D8 to PHY Register 0xFA
      4. Write 0x0301 to PHY Register 0xFB