LP PHY TX Power Control Init

(5.10.56.46 version)

1. Create an LP PHY table with width = 32, PHY width = 32. length = 1, and offset = 0
2. Establish a lpphy_txgains struct called gains

3. If this device has hardware power control (Board flags & 0x10000 == 0)

   1. If the band is 2GHz
      1. Set gains.gm_gain to 4
      2. Set gains.pga_gain to 12
      3. Set gains.pad_gain to 12
   2. Otherwise
      1. Set gains.gm_gain to 7
      2. Set gains.pga_gain to 15
      3. Set gains.pad_gain to 14
   3. Set bbmult to 150
   4. Set gains.dac_gain to 0

   5. Call LP PHY Set TX Gain with gains as argument

   6. Call LP PHY Set BBMult with bbmult as argument

4. Otherwise

   1. Call LP PHY Clear TX Power Offsets

   2. If the PHY revision is less than 2
      1. Set the table ID to 10
   3. Otherwise
      1. Set the table ID to 7
   4. Set the table data pointer to integer "ind"
   5. Loop on ind from 0 to 63 (inclusive) in steps of 1

      1. Write the LP table

      2. Increment the table offset

   6. MaskSet PHY Register 0x4A5 with mask 0xFF00 and set with 0xFF

   7. MaskSet PHY Register 0x4A5 with mask 0x8FFF and set with 0x5000

   8. MaskSet PHY Register 0x4A6 with mask 0xFFC0 and set with 0x1F

   9. If the PHY revision is less than 2
      1. If the PHY revision is 1
         1. Maskset PHY Register 0x43F with mask 0xFFF8 and set with 0x4

      2. Bitwise AND PHY Register 0x448 with mask 0xEFFF

      3. Bitwise OR PHY Register 0x448 with 0x2000

   10. Otherwise

       1. Bitwise AND PHY Register 0x503 with mask 0xFFFE

       2. Bitwise OR PHY Register 0x503 with 4

       3. Bitwise OR PHY Register 0x503 with 0x10

       4. Read Radio Register 0x121, bitwise AND with 0xF3, and bitwise OR with 1

       5. Write the previous result to Radio Register 0x121

       6. Call LP PHY Set TSSI Mux with argument 1

   11. Bitwise OR PHY Register 0x4A6 with 0x8000

   12. Write 0xA to PHY Register 0x4A8

   13. Bitwise AND PHY Register 0x4A4 with mask 0xFF80

   14. Bitwise AND PHY Register 0x4A5 with mask 0xF8FF

   15. MaskSet PHY Register 0x4A4 with mask 0x1FFF and set with 0x8000

   16. If the PHY revision >= 2

       1. Call Enable Bluetooth Coexistence Override

       2. Call LP PHY Set TX Gain Override with argument 1

   17. Bitwise OR PHY Register 0x44C with 0x1000

   18. Bitwise AND PHY Register 0x44D with mask 0xEFFF

   19. Perform do_dummy_tx(..., 0x1, 0x1)

   20. Read PHY Register 0x4AB and save as tmp

   21. If lpphy_cck_papd_disabled

       1. Maskset PHY Register 0x4A8 with mask 0xFF00 and set with 0x0600
   22. Otherwise
       1. Clear bits 0xFF in PHY Register 0x4A8
   23. If tmp bitwise ANDed with 0x8000 is not equal to 0
       1. Bitwise AND tmp with 0xFF, subtract 32, and save as the new value of tmp

       2. MaskSet PHY Register 0x4A6 with mask 0xFFC0 and set with tmp

   24. Bitwise AND PHY Register 0x44C with mask 0xEFFF

   25. Set lpphy_target_tx_freq to 0

   26. Call LP PHY Set TX Power Control with 0xE000 as argument