## LP PHY Set RX Gain (u32 gain)

- If PHY revision is less than 2
- Bitwise AND gain with 1, save as trsw
- Calculate the gain bitwise ANDed with 0xFFFC
- Calculate the gain bitwise ANDed with 0xC, right shifted by 2
- Save the bitwise OR of the two previous steps as lna
Set ext_lna to (gain bitwise ANDed with 2 >> 1)

Maskset PHY Register 0x44D with mask 0xFFFE and set with trsw

Maskset PHY Register 0x4B1 with mask 0xFBFF and set with ext_lna left shifted by 10

Maskset PHY Register 0x4B1 with mask 0xF7FF and set with ext_lna left shifted by 11

Write lna to PHY Register 0x4B6

- Otherwise
- Bitwise AND gain with 0xFFFF, save result as low_gain
- Right shift gain by 16, bitwise AND with 0xF and save as high_gain
- Right shift gain by 0x15, bitwise AND with 1, and save as ext_lna
- Right shift gain by 2, bitwise AND with 3, and save as tmp
If gain bitwise ANDed with (1 << 20) is zero

- Set trsw to 1

- Otherwise
- Set trsw to 0

Maskset PHY Register 0x44D with mask 0xFFFE and set with trsw

Maskset PHY Register 0x4B1 with mask 0xFDFF and set with ext_lna left shifted by 9

Maskset PHY Register 0x4B1 with mask 0xFBFF and set with ext_lna left shifted by 10

Write low_gain to PHY Register 0x4B6

Maskset PHY Register 0x4B7 with mask 0xFFF0 and set with high_gain

- If the current band is 2 GHz
Maskset PHY Register 0x4B1 with mask 0xE7FF and set with tmp left shifted by 11

Maskset PHY Register 0x4E6 with mask 0xFFE7 and set with tmp left shifted by 3

Call LP PHY RX Gain Override Enable with argument 1