LP PHY Synch STX

(Updated to 5.10.56.46).

1. Maskset Radio Register 0x04 with mask 0xFF07 and set with 0xFF (This seems to write 0xFF to the RR.)
2. Write 0xFF to Radio Register 0x05
3. Write 0xFF to Radio Register 0x06
4. Write 0xFF to Radio Register 0x07
5. Maskset Radio Register 0x08 with mask 0xFFF8 and set with 0xFF
6. For each entry in the table below:
   1. Compute a mask from the 'Mask' entry left shifted by the 'PHY Shift' entry

   2. Read the Radio Register with address given by the 'RF Addr' entry, right shift by the 'RF Shift' entry, and left shift by the 'PHY Shift' entry

   3. MaskSet the PHY Register with address given by 0x4F2 + 'PHY Offset'. The mask is the ones complement of the result from step a, and the value set is the result of step b.

7. Clear bits 0x7 in Radio Register 0x04
8. Write 0 to Radio Register 0x05
9. Write 0 to Radio Register 0x06
10. Write 0 to Radio Register 0x07
11. Clear bits 0x7 in Radio Register 0x08

Synch STX Table