bcm-v4

[Specification

GPHY All Gains ( u16 lna, u16 pga, int tr, bool itx)

  1. If PHY revision is 1
    1. Set addr to 0x414
    2. Set offset to 16
  2. Otherwise
    1. Set addr to 0x401
    2. Set offset to 8
  3. If the board flags have bit 0x1000 set and PHY revision >= 7

    1. Set bit 0x0800 in PHY Register 0x811

    2. If lna is 3
      1. Set lna to 2
      2. Clear bit 0x8000 in PHY Register 0x812

    3. Otherwise
      1. Set bit 0x8000 in PHY Register 0x812

  4. Loop 4 times with i as loop index
    1. Call APHY Write Table Entry with ( addr, i, lna ) as arguments

  5. Loop 16 times with i as loop index
    1. Call APHY Write Table Entry with ( addr, i + offset, lna ) as arguments

  6. If tr is not -1
    1. Call GPHY TR Switch with ( tr, 0 ) as arguments

  7. If itx
    1. Save PHY Registers 0x811 and 0x812

    2. Clear bit 0x0004 in PHY Register 0x812

    3. Set bit 0x0004 in PHY Register 0x811

    4. Do a Dummy Transmission with arguments ( 0, 1 )

    5. Restore PHY Registers 0x811 and 0x812

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Exported/Archived from the wiki to HTML on 2016-10-27