Finding the NRSSI Slope

1. If the Radio Revision is 9 or greater
   1. Return, there's nothing to do
2. If the Radio Revision is 8

   1. Write the saved NRSSI Slope Offset to Radio Register 0x7B

3. Disable Collision Resolution Signaling in the A PHY CRS0 Register (0x429) by unsetting bit 0x8000

4. Unset the CCK and ODFM bits in the Classify Control G PHY Extended Register (0x802)

5. Backup Core Register 0x3E2

6. OR Core Register 0x3E2 with 0x8000

7. Backup Core Registers 0x3E6 and 0x3F4

8. Backup Radio Registers 0x7A, 0x52, and 0x43

9. Backup PHY Registers 0x15, 0x5A, 0x59 and 0x58

10. If Hardware Power Control is enabled

    1. Backup PHY Registers 0x2E, 0x2F, 0x80F, 0x810, 0x801, 0x60, 0x14 and 0x478

    2. Write 0 to PHY Register 0x2E

    3. Write 0 to PHY Register 0x2F

    4. Write 0 to PHY Register 0x80F

    5. Write 0 to PHY Register 0x810

    6. Write 0x100 to PHY Register 0x478

    7. Write 0x40 to PHY Register 0x801

    8. Write 0x40 to PHY Register 0x60

    9. Write 0x200 to PHY Register 0x14

11. OR Radio Register 0x7A with 0x70

12. Set All G PHY Gains with an LNA value of 0, a PGA value of 8, a TR value of 0

13. AND Radio Register 0x7A with 0xF7

14. If the PHY Revision is 2 or greater

    1. OR PHY Register 0x811 with 0x30

    2. MaskSet PHY Register 0x812 with mask 0xFFCF and set with 0x10

15. OR Radio Register 0x7A with 0x80

16. Delay for 20 uSec

17. Read PHY Register 0x47F and right shift this value by 8, this is the Maximum RSSI value

18. AND the Maximum RSSI value with 0x3F
19. If the Maximum RSSI value is 0x20 or greater
    1. Subtract 0x40 from the Maximum RSSI value

20. AND Radio Register 0x7A with 0x7F (changed from 0x80 based on 4.174.64.19)

21. If the Analog Core Revision is 2 or greater

    1. MaskSet PHY Register 0x3 with mask 0xFF9F and set with 0x40

22. OR Core Register 0x3F4 with 0x2000

23. OR Radio Register 0x7A with 0xF

24. Write 0xF330 to PHY Register 0x15

25. If the PHY Revision is 2 or greater

    1. MaskSet PHY Register 0x812 with mask 0xFFCF and set with 0x20

    2. MaskSet PHY Register 0x811 with mask 0xFFCF and set with 0x20

26. Set All G PHY Gains with an LNA value of 3, a PGA value of 0, a TR value of 1

27. If the Radio Revision is 8

    1. Write 0x1F to Radio Register 0x43

28. Otherwise

    1. MaskSet Radio Register 0x52 with mask 0xFF0F and set 0x60

    2. MaskSet Radio Register 0x43 with mask 0xFFF0 and set 0x9

29. Write 0x480 to PHY Register 0x5A

30. Write 0x810 to PHY Register 0x59

31. Write 0xD to PHY Register 0x58

32. Delay for 20 uSec

33. Read PHY Register 0x47F and right shift this value by 8, this is the Minimum RSSI value

34. AND the Minimum RSSI value with 0x3F
35. If the Minimum RSSI value is 0x20 or greater
    1. Subtract 0x40 from the Minimum RSSI value
36. If the Minimum RSSI value equals the Maximum RSSI value
    1. The NRSSI Slope Scale is 0x10000
37. Otherwise
    1. The NRSSI Slope Scale is 0x400000 / (the Maximum RSSI value - the Minimum RSSI value)

38. If the Maximum RSSI value is >= -4

    1. Save the Maximum and Minimum RSSI values for use later
39. If Hardware Power Control is enabled

    1. Restore PHY Registers 0x2E, 0x2F, 0x80F, 0x810

40. Restore Radio Register 0x7A

41. Restore Core Register 0x3E2

42. Restore PHY Register 0x15

43. If the PHY Revision is 2 or greater

    1. AND PHY Register 0x812 with 0xFFCF

    2. AND PHY Register 0x811 with 0xFFCF

44. Restore Core Registers 0x3E6 and 0x3F4

45. Restore Radio Registers 0x52 and 0x43

46. Restore PHY Registers 0x5A, 0x59 and 0x58

47. Perform a SynthPU Workaround with the current channel

48. Set the CCK and ODFM bits in the Classify Control G PHY Extended Register (0x802)

49. Set the G PHY Original Gains

50. Enable Collision Resolution Signaling in the A PHY CRS0 Register (0x429) by setting bit 0x8000

51. If Hardware Power Control is enabled

    1. Restore PHY Registers 0x801, 0x60, 0x14 and 0x478

52. NRSSI Table Modification
53. Set NRSSI Threshold

Setting the NRSSI Threshold

1. If (Core Flags doesn't have the G Mode Enable flag (0x20000000) set and the PHY Revision isn't 2 or greater) or Board Flags doesn't have the ADC RSSI divider flag set

   1. Read the G PHY NRSSI table entry 32 (signed 6-bit value!)
   2. If the absolute value of the table entry value is 3 or larger
      1. The N1 Threshold and N2 Threshold values are -21 and -19 respectively
   3. Otherwise
      1. The N1 Threshold and N2 Threshold values are -25 and -21 respectively
2. Otherwise, the N1 Threshold and N2 Threshold have to be calculated as follows:
   1. Start with B1 Threshold and B2 Threshold of -13 and -10 respectively
   2. If the interference mitigation is set to non-WLAN
      1. The B1 Threshold and B2 Thresholds are -13 and -17 respectively
   3. If the interference mitigation is in Automatic or Manual mode and FIXME
      1. The B1 Threshold and B2 Thresholds are -8 and -9 respectively
   4. Find the difference between the saved Maximum RSSI and the saved Minimum RSSI. this is the RSSI Delta
   5. Add 0x1B to the B1 Threshold value and multiply by the RSSI Delta, this is the N1 Threshold value
   6. Add the Minimum RSSI value left shifted by 6 to the N1 Threshold value
   7. If the N1 Threshold value is less than 0
      1. FIXME
   8. Otherwise
      1. FIXME
   9. Divide the N1 Threshold value by 64
   10. Add 0x1B to the B2 Threshold value and multiply by the RSSI Delta, this is the N2 Threshold value
   11. Add the Minimum RSSI value left shifted by 6 to the N2 Threshold value
   12. If the N2 Threshold value is less than 0
       1. FIXME
   13. Otherwise
       1. FIXME
   14. Divide the N2 Threshold value by 64
   15. Clamp the N1 and N2 Threshold values between [-32,31]
3. Left shift the N1 Threshold value AND'd with 0x3F by 6 and OR the result with the N2 Threshold value AND'd with 0x3F

4. MaskSet PHY Register 0x48A with mask 0xF000 and set with the result

Update the NRSSI Table

Take each value of the NRSSI table (note that they are 6-bit signed values!), subtract the desired delta and write it back (noting that it must be clamped to a signed 6-bit value!)