Clock Control (u32 mode)

1. If PMU Present (core revision >= 20)

   1. If clk

      1. If mode equals 0
         1. Set bit 2 in MMIO Register 0x1E0
         2. Delay 33 usec
         3. Spin wait for 0x20000 to be clear in MMIO Register 0x1E0, test every 10 usec, max of 1500 tries
         4. Warn if loop expires and bit 0x20000 in 0x1E0 is still set
      2. Otherwise

         1. If (the PMU Revision is 0) and (MMIO Register 0x1E0 & 0x12 is not zero)

            1. Spin wait for 0x20000 to be clear in MMIO Register 0x1E0, test every 10 usec, max of 1500 tries
            2. Clear bit 0x2 in MMIO Register 0x1E0

   2. Set forcefastclk to (mode == 0)

2. Otherwise
   1. Initialize a bool wakeup to false
   2. Set wakeup to true if the core revision is less than 9

   3. If up and wakeup are both true

      1. Call PHY Ucode Wake Override Set with 1 as argument

   4. Call Clock Control CC with mode as argument and save result as forcefastclk

   5. If the core revision is less than 11

      1. If forcefastclock

         1. Call Mhf with 0, 0x400, 0x400, 3 as arguments

      2. Otherwise

         1. Call Mhf with 0, 0x400, 0, 3 as arguments

   6. If forcefastclk

      1. Set bit 0x10 in wake_override

   7. Otherwise

      1. Clear bit 0x10 in wake_override

   8. If up and wakeup

      1. Call PHY Ucode Wake Override Clear with 1 as argument