This ensures that the chip is working, memory accesses work and side effects trigger correctly.

  1. Backup the 32 bit contents of shared memory word 0.
  2. Write the value 0x55aaaa55 to that shared memory location and read it back to test for endianness problems.
  3. repeat with 0xaa5555aa.
  4. restore the original value
  5. for core revisions 3 through 10:
    1. write 0xAAAA as a 16-bit value to the usually 32-bit register "TSF Contention Free Period Start" (0x18c)

    2. write the 32-bit value 0xccccbbbb to the same register
    3. verify that 0xcccc and 0xbbbb are read back from the "TSF CFP Start High"/Low registers (0x604, 0x606), the 32-bit register shadows these two 16-bit registers but with update side effects

  6. clear TSF CFP start (0x18c)

  7. validate that MAC control has bit "IHR Region Enabled" and possibly "G Mode" set.

Exported/Archived from the wiki to HTML on 2016-10-27