gmac_enable
- read Gmac core reg cmdcfg
call gmac_init_reset
- set CC_SR bit in cmdcfg
- unset CC_RE and CC_TE bit in cmdcfg
- write cmdcfg back into Gmac core reg
call gmac_clear_reset
- sleep 2 usec
- unset CC_SR bit in cmdcfg
- set CC_RE and CC_TE bit in cmdcfg
- write cmdcfg back into Gmac core reg
- mask devstatus with DS_MM_MASK and shift it to the right by DS_MM_SHIFT, write result into var mode
- if chipid is not 47162 or mode is not 0
- set bit CS_FH in gmac core reg clk_ctl_st
- if chipid is 47162 and mod is 2
- call si_pmu_chipcontrol with sih, PMU_CHIPCTL1, PMU_CC1_RXC_DLL_BYPASS and PMU_CC1_RXC_DLL_BYPASS (source: brcm/shared/hndpmu.c)
- if chipid is 0x5357 or chipid is 0x4749 or chipid is 53572 or chipid is 0x4716 or chipid is 47162
- set var flctl to 0x03cb04cb
- if chipid is 0x5357 or chipid is 0x4749 or chipid is 53572
- set var flctl to 0x2300e1
- write var flctl into gmac core reg flowctlthresh
- write 0x27fff into gmac core reg pausectl
- red gmac core reg rxqctl into var rxqctl
- unset RC_MDP_MASK mask in var rxqctl
- call si_clock, device the result by 1000000 and write it into var bp_clk (source: brcm/shared/siutils.c)
- multiply bp_clk by 128, divide the result by 1000, subtract 3 and write the result into mdp
- OR rxqctl with mdp shifted by RC_MDP_SHIFT to the left
- write var rxqctl into gmac core reg rxqctl