bcm-v4

[Specification

GMAC Register

These registers are in the normal memory space of the GMAC core.

Offset

Size

Name/Function

Description

0x000

4

devcontrol

0x004

4

devstatus

configuration of the interface

HOLE

0x00c

4

biststatus

HOLE

0x020

4

intstatus

interrupt status

0x024

4

intmask

interrupt mask

0x028

4

gptimer

HOLE

0x100

4

intrecvlazy

0x104

4

flowctlthresh

flow control thresholds

0x108

4

wrrthresh

0x10c

4

gmac_idle_cnt_thresh

HOLE

0x180

4

phyaccess

phy access address

HOLE

0x188

4

phycontrol

phy control address

0x18c

4

txqctl

0x190

4

rxqctl

0x194

4

gpioselect

0x198

4

gpio_output_en

HOLE

0x1e0

4

clk_ctl_st

0x1e4

4

hw_war

0x1e8

4

pwrctl

HOLE

0x200

DMA Regs

0x300

GMAC MIB Regs

HOLE

0x800

4

unimacversion

0x804

4

hdbkpctl

0x808

4

cmdcfg

configuration

0x80c

4

macaddrhigh

high 4 octets of own mac address

0x810

4

macaddrlow

low 2 octets of own mac address

0x814

4

rxmaxlength

max receive frame length with vlan tag

0x818

4

pausequanta

HOLE

0x844

4

macmode

0x848

4

outertag

0x84c

4

innertag

HOLE

0x85c

4

txipg

HOLE

0xb30

4

pausectl

0xb34

4

txflush

0xb38

4

rxstatus

0xb3c

4

txstatus

devcontrol Register

Offset

Name/Function

Description

0x00000002

DC_TSM

0x00000004

DC_CFCO

0x00000008

DC_RLSS

0x00000010

DC_MROR

0x00000060

DC_FCM_MASK

5

DC_FCM_SHIFT

0x00000080

DC_NAE

0x00000100

DC_TF

0x00030000

DC_RDS_MASK

16

DC_RDS_SHIFT

0x000c0000

DC_TDS_MASK

18

DC_TDS_SHIFT

devstatus Register

Offset

Name/Function

Description

0x00000001

DS_RBF

0x00000002

DS_RDF

0x00000004

DS_RIF

0x00000008

DS_TBF

0x00000010

DS_TDF

0x00000020

DS_TIF

0x00000040

DS_PO

0x00000300

DS_MM_MASK

Mode of the interface

8

DS_MM_SHIFT

intstatus Register

Offset

Name/Function

Description

0x00000001

I_MRO

0x00000002

I_MTO

0x00000004

I_TFD

0x00000008

I_LS

0x00000010

I_MDIO

0x00000020

I_MR

0x00000040

I_MT

0x00000080

I_TO

0x00000400

I_PDEE

descriptor error

0x00000800

I_PDE

data error

0x00001000

I_DE

descriptor protocol error

0x00002000

I_RDU

receive descriptor underflow

0x00004000

I_RFO

receive fifi overflow

0x00008000

I_XFU

transmit fifo underflow

0x00010000

I_RI

Interrupt for RX queue 0

0x01000000

I_XI0

Interrupt for TX queue 0

0x02000000

I_XI1

Interrupt for TX queue 1

0x04000000

I_XI2

Interrupt for TX queue 2

0x08000000

I_XI3

Interrupt for TX queue 3

0x0f01fcff

I_INTMASK

0x0000fc00

I_ERRMASK

intrecvlazy Register

Offset

Name/Function

Description

0x00ffffff

IRL_TO_MASK

0xff000000

IRL_FC_MASK

24

IRL_FC_SHIFT

shift the number of interrupts triggered per received frame

phyaccess Register

Offset

Name/Function

Description

0x0000ffff

PA_DATA_MASK

0x001f0000

PA_ADDR_MASK

16

PA_ADDR_SHIFT

0x1f000000

PA_REG_MASK

24

PA_REG_SHIFT

0x20000000

PA_WRITE

0x40000000

PA_START

phycontrol Register

Offset

Name/Function

Description

0x0000001f

PC_EPA_MASK

0x007f0000

PC_MCT_MASK

16

PC_MCT_SHIFT

0x00800000

PC_MTE

clk_ctl_st Register

Offset

Name/Function

Description

0x00000001

CS_FA

0x00000002

CS_FH

0x00000004

CS_FI

0x00000008

CS_AQ

0x00000010

CS_HQ

0x00000020

CS_FC

0x00000100

CS_ER

0x00010000

CS_AA

0x00020000

CS_HA

0x00040000

CS_BA

0x00080000

CS_BH

0x01000000

CS_ES

cmdcfg Register

Offset

Name/Function

Description

0x00000001

CC_TE

set to activate TX

0x00000002

CC_RE

set to activate RX

0x0000000c

CC_ES_MASK

Ethernet speed see gmac_speed

2

CC_ES_SHIFT

0x00000010

CC_PROM

set to activate promiscuous mode

0x00000020

CC_PAD_EN

0x00000040

CC_CF

0x00000080

CC_PF

0x00000100

CC_RPI

unset to enable 802.3x tx flow control

0x00000200

CC_TAI

0x00000400

CC_HD

set if in half duplex mode

10

CC_HD_SHIFT

0x00000800

CC_SR

set to reset mode

0x00008000

CC_ML

set to activate mac loopback mode

0x00400000

CC_AE

0x00800000

CC_CFE

0x01000000

CC_NLC

0x02000000

CC_RL

0x04000000

CC_RED

0x08000000

CC_PE

0x10000000

CC_TPI

0x20000000

CC_AT

GMAC MIB Register

The offsets are relative to the GMAC core memory space beginning.

Offset

Size

Name/Function

Description

0x300

4

tx_good_octets

0x304

4

tx_good_octets_high

0x308

4

tx_good_pkts

0x30c

4

tx_octets

0x310

4

tx_octets_high

0x314

4

tx_pkts

0x318

4

tx_broadcast_pkts

0x31c

4

tx_multicast_pkts

0x320

4

tx_len_64

0x324

4

tx_len_65_to_127

0x328

4

tx_len_128_to_255

0x32c

4

tx_len_256_to_511

0x330

4

tx_len_512_to_1023

0x334

4

tx_len_1024_to_1522

0x338

4

tx_len_1523_to_2047

0x33c

4

tx_len_2048_to_4095

0x340

4

tx_len_4095_to_8191

0x344

4

tx_len_8192_to_max

0x348

4

tx_jabber_pkts

Error

0x34c

4

tx_oversize_pkts

Error

0x350

4

tx_fragment_pkts

0x354

4

tx_underruns

Error

0x358

4

tx_total_cols

0x35c

4

tx_single_cols

0x360

4

tx_multiple_cols

0x364

4

tx_excessive_cols

Error

0x368

4

tx_late_cols

Error

0x36c

4

tx_defered

0x370

4

tx_carrier_lost

0x374

4

tx_pause_pkts

0x378

4

tx_uni_pkts

0x37c

4

tx_q0_pkts

0x380

4

tx_q0_octets

0x384

4

tx_q0_octets_high

0x388

4

tx_q1_pkts

0x38c

4

tx_q1_octets

0x390

4

tx_q1_octets_high

0x394

4

tx_q2_pkts

0x398

4

tx_q2_octets

0x39c

4

tx_q2_octets_high

0x3a0

4

tx_q3_pkts

0x3a4

4

tx_q3_octets

0x3a8

4

tx_q3_octets_high

HOLE

0x3b0

4

rx_good_octets

0x3b4

4

rx_good_octets_high

0x3b8

4

rx_good_pkts

0x3bc

4

rx_octets

0x3c0

4

rx_octets_high

0x3c4

4

rx_pkts

0x3c8

4

rx_broadcast_pkts

0x3cc

4

rx_multicast_pkts

0x3d0

4

rx_len_64

0x3d4

4

rx_len_65_to_127

0x3d8

4

rx_len_128_to_255

0x3dc

4

rx_len_256_to_511

0x3e0

4

rx_len_512_to_1023

0x3e4

4

rx_len_1024_to_1522

0x3e8

4

rx_len_1523_to_2047

0x3ec

4

rx_len_2048_to_4095

0x3f0

4

rx_len_4095_to_8191

0x3f4

4

rx_len_8192_to_max

0x3f8

4

rx_jabber_pkts

Error

0x3fc

4

rx_oversize_pkts

Error

0x400

4

rx_fragment_pkts

0x404

4

rx_missed_pkts

Error

0x408

4

rx_crc_align_errs

Error

0x40c

4

rx_undersize

Error

0x410

4

rx_crc_errs

Error

0x414

4

rx_align_errs

Error

0x418

4

rx_symbol_errs

Error

0x41c

4

rx_pause_pkts

0x420

4

rx_nonpause_pkts

0x424

4

rx_sachanges

0x428

4

rx_uni_pkts

DMA Registers

It uses the same DMA Code as wl uses and on which brcsmac is based on. For more information have a look at DMA64. It uses 4 DMA controllers at the following addresses: 0x200, 0x240, 0x280 and 0x2C0. The first address has a TX and RX controller and the other just have a TX controller.

The DMA functions are released under an open source license by Broadcom and can be found in brcm/shared/hnddma.c and brcm/include/sbhnddma.h.

GMAC Common Core Registers

These registers are in the normal memory space of the GMAC Common core.

Offset

Size

Name/Function

0x000

4

stag0

0x004

4

stag1

0x008

4

stag2

0x00c

4

stag3

HOHL

0x020

4

parsercontrol

0x024

4

mib_max_len

HOHL

0x100

4

phyaccess

0x104

4

phycontrol

HOHL

0x110

4

gmac0_rgmii_cntl

HOHL

0x200

4

cfp_access

HOHL

0x210

4

cfp_tcam_data0

0x214

4

cfp_tcam_data1

0x218

4

cfp_tcam_data2

0x21c

4

cfp_tcam_data3

0x220

4

cfp_tcam_data4

0x224

4

cfp_tcam_data5

0x228

4

cfp_tcam_data6

0x22c

4

cfp_tcam_data7

0x230

4

cfp_tcam_mask0

0x234

4

cfp_tcam_mask1

0x238

4

cfp_tcam_mask2

0x23c

4

cfp_tcam_mask3

0x240

4

cfp_tcam_mask4

0x244

4

cfp_tcam_mask5

0x248

4

cfp_tcam_mask6

0x24c

4

cfp_tcam_mask7

0x250

4

cfp_action_data

HOHL

0x2a0

4

tcam_bist_cntl

0x2a4

4

tcam_bist_status

0x2a8

4

tcam_cmp_status

0x2ac

4

tcam_disable

HOHL

0x2f0

4

tcam_test_cntl

HOHL

0x300

4

udf_0_a3_a0

0x304

4

udf_0_a7_a4

0x308

4

udf_0_a8

HOHL

0x310

4

udf_1_a3_a0

0x314

4

udf_1_a7_a4

0x318

4

udf_1_a8

HOHL

0x320

4

udf_2_a3_a0

0x324

4

udf_2_a7_a4

0x328

4

udf_2_a8

HOHL

0x330

4

udf_0_b3_b0

0x334

4

udf_0_b7_b4

0x338

4

udf_0_b8

HOHL

0x340

4

udf_1_b3_b0

0x344

4

udf_1_b7_b4

0x348

4

udf_1_b8

HOHL

0x350

4

udf_2_b3_b0

0x354

4

udf_2_b7_b4

0x358

4

udf_2_b8

HOHL

0x360

4

udf_0_c3_c0

0x364

4

udf_0_c7_c4

0x368

4

udf_0_c8

HOHL

0x370

4

udf_1_c3_c0

0x374

4

udf_1_c7_c4

0x378

4

udf_1_c8

HOHL

0x380

4

udf_2_c3_c0

0x384

4

udf_2_c7_c4

0x388

4

udf_2_c8

HOHL

0x390

4

udf_0_d3_d0

0x394

4

udf_0_d7_d4

0x394

4

udf_0_d11_d8

Phy Registers

Offset

Name/Function

Description

(1 << 15)

CTL_RESET

reset

(1 << 14)

CTL_LOOP

loopback

(1 << 13)

CTL_SPEED

(1 << 12)

CTL_ANENAB

enable autonegotiation

(1 << 9)

CTL_RESTART

restart autonegotiation

(1 << 8)

CTL_DUPLEX

duplex mode

(1 << 6)

CTL_SPEED_MSB

Offset

Name/Function

Description

(0 << 6) | (0 << 13)

CTL_SPEED_10

Ethernet speed to 10MBit/s

(0 << 6) | (1 << 13)

CTL_SPEED_100

Ethernet speed to 100MBit/s

(1 << 6) | (0 << 13)

CTL_SPEED_1000

Ethernet speed to 1000MBit/s

Offset

Name/Function

Description

(1 << 6)

ADV_10FULL

advertise 10MBits/s full duplex

(1 << 5)

ADV_10HALF

advertise 10MBits/s half duplex

(1 << 8)

ADV_100FULL

advertise 100MBits/s full duplex

(1 << 7)

ADV_100HALF

advertise 100MBits/s half duplex

Offset

Name/Function

Description

0x0100

ADV_1000HALF

advertise 1000MBits/s half duplex

0x0200

ADV_1000FULL

advertise 1000MBits/s full duplex


Exported/Archived from the wiki to HTML on 2016-10-27