The SPROM is uint16 based and all reads and writes to the SPROM should be done in 16 bit transactions. The SPROM is accessed through the Backplane Registers, starting at offset 0x1000. Offsets given here are byte offsets from the beginning of the SPROM. As an example, il0macaddr is found at Backplane Register 0x1048 (0x1000 + 0x48). Unprogrammed values default to 0xFFFF.

SPROM Layouts

For versions 1-3, the SPROM size is 128 bytes. For versions 4, 5 and 8, the size is 440 bytes. Versions 6 and 7 have not been seen. The maximum possible SPROM size is 512 bytes.

For SPROM versions 1-3, the layout may be determined by reading 128 bytes and checking the CRC8. If it passes, the SPROM Revision is found at offset 0x7E. If it doesn't pass the CRC8, it may be SPROM version 4 or higher with special signature values that may be checked to determine the version. An equally valid method is to read 440 bytes and check the CRC8. If it passes this test, the revision is found at offset 0x1B6, otherwise, the contents are invalid.

Revision 1 SPROM

Offset

Size

Usage

Notes

0x04

2

Subsytem product ID for PCI

0x06

2

Subsystem vendor ID for PCI

0x08

2

Product ID for PCI

Named Parameter Area

0x48

6

il0macaddr - MAC address for 802.11b/g

0x4E

6

et0macaddr - MAC address for ethernet

See b44 Driver

0x54

6

et1macaddr - MAC address for 802.11a

Ethernet PHY settings: one or two singles or a dual (encoded bitwise), see b44 Driver

0x5A

2

bits 4-0: et0phyaddr - MII Address for enet0

0x1F if not present

bits 9-5: et1phyaddr - MII Address for enet1

0x1F if not present

bit 14: et0mdcport - MDIO for enet0

bit 15: et1mdcport - MDIO for enet1

Board revision, Antennas 0/1, Country Code

0x5C

2

bits 7-0: Board Revision

bits 11-8: Country Code

bits 13-12: Bitfield of antennas available for A PHY

bits 15-14: Bitfield of antennas available for B/G PHY

0x5E

2

pa0b0

0x60

2

pa0b1

0x62

2

pa0b2

0x64

2

GPIO 0 and 1

See GPIO below

0x66

2

GPIO 2 and 3

See GPIO below

PA Max Power (Units: 4*dBm (dBm in Q5.2))

0x68

2

bits 7-0: A PHY Max Power

bits 15-8: B/G PHY Max Power

0x6A

2

pa1b0

0x6C

2

pa1b1

0x6E

2

pa1b2

Idle TSSI Target

0x70

2

bits 7-0: A PHY

bits 15-8: B/G PHY

0x72

2

Low 16 bits of Board Flags

If unset (0xFFFF) use 0

Antenna Gain If unset, use 2 dBm, all values are in dBm

0x74

2

bits 7-0: A PHY

bits 15-8: B/G PHY

0x76

8

OEM String

SROM Rev 1 only

SPROM Checksum and Revision

0x7E

2

bits 7-0: SPROM Revision

bits 15-8: SPROM CRC8

Revision 2 SPROM

/!\ Same as Revision 1 unless specified here

Offset

Size

Usage

Notes

0x38

2

High 16 bits of BoardFlags

A PHY Max Power

0x3A

2

bits 7-0: Max Power High

bits 15-8: Max Power Low

0x3C

2

pa1lob0: A PHY PA Low Settings

0x3E

2

pa1lob1: A PHY PA Low Settings

0x40

2

pa1lob2: A PHY PA Low Settings

0x42

2

pa1hib0: A PHY PA High Settings

0x44

2

pa1hib1: A PHY PA High Settings

0x46

2

pa1hib2: A PHY PA High Settings

Antenna Gain

0x74

2

bits 7-0: A PHY

bits 15-8: B/G PHY

opo: OFDM Power Offset from CCK Level

0x78

2

bits 7-0: OFDM Power Offset from CCK Level

bits 15-8: Unused

0x7C

2

Country Code

2 Characters, 0 if unset

Antenna gain is stored with granularity of 0.25 dBm as follows:

Mask

Value

0xC0

Fractional part, this many quarter dBm (unsigned)

0x3F

Whole dBm part (signed)

So, the stored value is found by: Whole + Fractional/4.

Revision 3 SPROM

/!\ Same as Revision 2 unless specified here

Offset

Size

Usage

Notes

0x2C

4

ofdmapo: A PHY OFDM middle subband Power Offset

Big-Endian

0x30

4

ofdmalpo: A PHY OFDM low subband Power Offset

Big-Endian

0x34

4

ofdmahpo: A PHY OFDM high subband Power Offset

Big-Endian

GPIO LED Powersave Duty Cycle (Big-Endian)

0x42

4

bits 31-24: On Count

bits 23-16: Unused

bits 15-8: Off Count

bits 7-0: Unused

cckpo - CCK Power Offset

0x78

2

bits 3-0: CCK Rate 1M Power Offset

bits 7-4: CCK Rate 2M Power Offset

bits 11-8: CCK Rate 5.5M Power Offset

bits 15-12: CCK Rate 11M Power Offset

0x7A

4

ofdmgpo - G PHY OFDM Power Offset, consists of 8 4-bit values for the OFDM bitrates starting 6M in the least significant nibble

Big-Endian

Revision 4 SPROM

/!\ This revision does not inherit from older layouts

Offset

Size

Usage

Notes

0x0004

2

Subsytem product ID for PCI

0x0006

2

Subsystem vendor ID for PCI

0x0008

2

Product ID for PCI

0x0040

2

SPROM Signature

Must be 0x5372 to be a valid v4 SPROM

0x0042

2

Board Revision

0x0044

4

Board Flags

0x0048

4

Board Flags 2

0x004C

6

MAC Address

0x0052

2

Country Code

Two characters

0x0054

2

Regulatory(?) Revision

0x0056

1

LED 0 Behaviour

0x0057

1

LED 1 Behaviour

0x0058

1

LED 2 Behaviour

0x0059

1

LED 3 Behaviour

0x005A

2

bits 15-8: LED Powersave Duty Cycle

On Count (value is right shifted by 24)

bits 7-0: LED Powersave Duty Cycle

Off Count (value is right shifted by 8)

0x005C

2

bits 7-0: 802.11B/G Antennas Available

Bitfield

bits 15-8: 802.11A Antenas Available

Bitfield

0x005E

1

Antenna 0 Gain

0x005F

1

Antenna 1 Gain

0x0060

1

Antenna 2 Gain

0x0061

1

Antenna 3 Gain

Fixed Power Indices when Power Control is disabled

0x0062

2

TX Power Index 2GHz

0x0064

2

TX Power Index 2GHz

0x0066

2

TX Power Index 5GHz middle subband

0x0068

2

TX Power Index 5GHz middle subband

0x006A

2

TX Power Index 5GHz low subband

0x006C

2

TX Power Index 5GHz low subband

0x006E

2

TX Power Index 5GHz high subband

0x0070

2

TX Power Index 5GHz high subband

Per Path Variables

0x0080

-

Path 1 Variables

0x00AE

-

Path 2 Variables

0x00DC

-

Path 3 Variables

0x010A

-

Path 4 Variables

Power Offsets

0x0138

2

2GHz CCK Power Offset

0x013A

4

2GHz OFDM Power Offset

0x013E

4

5GHz middle subband OFDM Power Offset

0x0142

4

5GHz low subband OFDM Power Offset

0x0146

4

5GHz high subband OFDM Power Offset

0x014A

2

2GHz MCS Power Offset

They may have reserved space for additional values

0x015A

2

5GHz MCS Power Offset

They may have reserved space for additional values

0x016A

2

5GHz low subband MCS Power Offset

They may have reserved space for additional values

0x017A

2

5GHz high subband MCS Power Offset

They may have reserved space for additional values

0x018A

2

CCD Power Offset

0x018C

2

STBC Power Offset

0x018E

2

BW40 Power Offset

0x0190

2

BWDUP Power Offset

0x01B6

2

bits 7-0: SROM Revision

Path Variables

Offsets are given as byte offsets from the start of the Path Variable section.

Offset

Size

Function

Notes

0x0000

2

bits 7-0: Max Power 2GHz

bits 15-8: ITT 2GHz

0x0002

2

2GHz Power Amplifier W0

0x0004

2

2GHz Power Amplifier W1

0x0006

2

2GHz Power Amplifier W2

0x0008

2

2GHz Power Amplifier W3

0x000A

2

bits 7-0: Max Power 5GHz

bits 15-8: ITT 5GHz

0x000C

1

5GHz high subband Power Amplifier Max

0x000D

1

5GHz low subband Power Amplifier Max

5 GHz Power Amplifier

0x000E

2

5GHz Power Amplifier (middle subband)

0x0010

2

5GHz Power Amplifier (middle subband)

0x0012

2

5GHz Power Amplifier (middle subband)

0x0014

2

5GHz Power Amplifier (middle subband)

0x0016

2

5GHz Power Amplifier (low subband)

0x0018

2

5GHz Power Amplifier (low subband)

0x001A

2

5GHz Power Amplifier (low subband)

0x001C

2

5GHz Power Amplifier (low subband)

0x001E

2

5GHz Power Amplifier (high subband)

0x0020

2

5GHz Power Amplifier (high subband)

0x0022

2

5GHz Power Amplifier (high subband)

0x0024

2

5GHz Power Amplifier (high subband)

Revision 5 SPROM

/!\ Same as Revision 4 unless specified here

Offset

Size

Usage

Notes

0x0004

2

Subsytem product ID for PCI

0x0006

2

Subsystem vendor ID for PCI

0x0008

2

Product ID for PCI

0x0042

2

Board Revision

0x004A

4

Board Flags

0x004E

4

Board Flags 2

0x0052

6

MAC Address

0x0044

2

Country Code

Two characters

0x0046

2

Regulatory(?) Revision

0x0076

1

LED 0 Behaviour

0x0077

1

LED 1 Behaviour

0x0078

1

LED 2 Behaviour

0x0079

1

LED 3 Behaviour

0x005A

2

bits 15-8: LED Powersave Duty Cycle

On Count (value is right shifted by 24)

bits 7-0: LED Powersave Duty Cycle

Off Count (value is right shifted by 8)

0x005C

2

bits 7-0: 802.11B/G Antennas Available

Bitfield

bits 15-8: 802.11A Antenas Available

Bitfield

0x005E

1

Antenna 0 Gain

0x005F

1

Antenna 1 Gain

0x0060

1

Antenna 2 Gain

0x0061

1

Antenna 3 Gain

Fixed Power Indices when Power Control is disabled

0x0062

2

TX Power Index 2GHz

0x0064

2

TX Power Index 2GHz

0x0066

2

TX Power Index 5GHz middle subband

0x0068

2

TX Power Index 5GHz middle subband

0x006A

2

TX Power Index 5GHz low subband

0x006C

2

TX Power Index 5GHz low subband

0x006E

2

TX Power Index 5GHz high subband

0x0070

2

TX Power Index 5GHz high subband

Revision 8 SPROM

/!\ This revision does not inherit from older layouts

Offset

Size

Usage

Notes

0x0004

2

Subsytem product ID for PCI

0x0006

2

Subsystem vendor ID for PCI

0x0008

2

Product ID for PCI

0x0020

96

48 word hardware header for PCIe rev >= 6

0x0080

2

SPROM Signature

Must be 0x5372 to be a valid v8 SPROM

0x0082

2

Board Revision

0x0084

4

Board Flags

0x0088

4

Board Flags 2

0x008C

6

MAC Address

0x0092

2

Country Code

Two characters

0x0094

2

Regulatory(?) Revision

0x0096

1

LED 0 Behaviour

0x0097

1

LED 1 Behaviour

0x0098

1

LED 2 Behaviour

0x0099

1

LED 3 Behaviour

0x009A

2

bits 15-8: LED Powersave Duty Cycle

On Count (value is right shifted by 24)

bits 7-0: LED Powersave Duty Cycle

Off Count (value is right shifted by 8)

0x009C

2

bits 7-0: 802.11B/G Antennas Available

Bitfield

bits 15-8: 802.11A Antenas Available

Bitfield

0x009E

1

Antenna 0 Gain

0x009F

1

Antenna 1 Gain

0x00A0

1

Antenna 2 Gain

0x00A1

1

Antenna 3 Gain

Fixed Power Indices when Power Control is disabled

0x0062

2

TX Power Index 2GHz

0x0064

2

TX Power Index 2GHz

0x0066

2

TX Power Index 5GHz middle subband

0x0068

2

TX Power Index 5GHz middle subband

0x006A

2

TX Power Index 5GHz low subband

0x006C

2

TX Power Index 5GHz low subband

0x006E

2

TX Power Index 5GHz high subband

0x0070

2

TX Power Index 5GHz high subband

Per Path Variables

0x00C0

-

Path 1 Variables

SISO PA parameters are here

0x00E0

-

Path 2 Variables

0x0100

-

Path 3 Variables

0x0120

-

Path 4 Variables

Power Offsets

0x0140

2

2GHz CCK Power Offset

0x0142

4

2GHz OFDM Power Offset

0x0146

4

5GHz middle subband OFDM Power Offset

0x014A

4

5GHz low subband OFDM Power Offset

0x014E

4

5GHz high subband OFDM Power Offset

0x0152

2

2GHz MCS Power Offset

They may have reserved space for additional values

0x0162

2

5GHz MCS Power Offset

They may have reserved space for additional values

0x0172

2

5GHz low subband MCS Power Offset

They may have reserved space for additional values

0x0182

2

5GHz high subband MCS Power Offset

They may have reserved space for additional values

0x0192

2

CCD Power Offset

0x0194

2

STBC Power Offset

0x0196

2

BW40 Power Offset

0x0198

2

BWDUP Power Offset

0x01B7

2

bits 7-0: SROM Revision

Legacy names for SISO PA parameters

Offsets are given as byte offsets from the start of the Path 1 Variables

Offset

Size

Function

Notes

0x0000

2

bits 7-0: Max Power 2GHz

bits 15-8: ITT 2GHz

0x0002

2

Power Amplifier W0 PAB0

0x0004

2

Power Amplifier W0 PAB1

0x0006

2

Power Amplifier W0 PAB2

0x0008

2

bits 7-0: Max Power 5GHz

bits 15-8: ITT 5GHz

0x000A

2

bits 7-0: LCHC 5GHz

bits 15-8: Max Power 5GHz

0x000C

2

5GHz Power Amplifier (middle subband) W1 PAB0

0x000E

2

5GHz Power Amplifier (middle subband) W1 PAB1

0x0010

2

5GHz Power Amplifier (middle subband) W1 PAB2

0x0012

2

5GHz Power Amplifier (low subband) W1 PAB0_LC

0x0014

2

5GHz Power Amplifier (low subband) W1 PAB1_LC

0x0016

2

5GHz Power Amplifier (low subband) W1 PAB2_LC

0x0018

2

5GHz Power Amplifier (high subband) W1 PAB0_HC

0x001A

2

5GHz Power Amplifier (high subband) W1 PAB1_HC

0x001C

2

5GHz Power Amplifier (high subband) W1 PAB2_HC

GPIO

If the value in the SPROM isn't 0 or 0xFFFF, the pin should be configured. GPIO pins 0 and 2 are stored in bits 7-0 of offsets 0x64 and 0x66 respectively. GPIO pins 1 and 3 are stored in bits 15-8 of offsets 0x64 and 0x66 respectively.

Calculating the CRC

The CRC value is a crc8 calculated over the first 127 bytes (that's all excluding the crc8 byte) in the SPROM (which is the crc8 byte) after byte-reversing each 16 bit word. The starting value for the crc8 is 0xFF and the final value is XOR'ed with 0xFF, the polynomial is x8+x7+x6+x4+x2+1.

Writing to the SPROM

In order to write to the SPROM, or the PCI config space SPROM Control register (pci config space 0x88) with 0x10 (WRITE ENABLE) and wait 500 msecs, then write each 16-bit word the the correct offset in the MMIO space delaying 20 msecs after each write. Then turn off the write enable bit again and again wait 500 msecs.

SPROM Contents versus Revision

Rev 3 inherits from Rev 2, which inherits from Rev 1. Rev 5 inherits from Rev 4.

Label

ssb label

Mask

Rev 1

Rev 2

Rev 3

Rev 4

Rev 5

Rev 8

aa2g

ant_available_bg

0x00FF

0x5C

0x9C

aa5g

ant_available_a

0xFF00

0x5C

0x9C

ag0

0x00FF

0x74

0x5E

0x9E

ag1

0xFF00

0x74

0x5E

0x9E

ag2

0x00FF

N/A

N/A

N/A

0x60

0xA0

ag3

0xFF00

N/A

N/A

N/A

0x60

0xA0

antswitch

0xFF00

N/A

N/A

N/A

0x7A

0xA2

boardflags

boardflags_lo

0x72

0x44

0x4A

0x84

boardflags2

boardflags_hi

N/A

0x38

0x46

0x4C

0x86

boardnum

0x48

0x4A

0x4C

0x56

0x90

boardrev

board_rev

0x00FF

0x5C

0x42

0x82

boardtype

0x04

0x04

0x04

bw40po

N/A

N/A

N/A

0x18E

0x196

bwduppo

N/A

N/A

N/A

0x190

0x198

bxa2g

0x52

0xA4

bxa5g

0x54

0xA6

cc

0x0F00

0x5C

N/A

N/A

N/A

cck2gpo

N/A

N/A

N/A

0x138

0x140

ccode

country_code

0x76

0x52

0x44

0x92

cddpo

N/A

N/A

N/A

0x18A

0x192

et0macaddr

et0mac

0x4E

N/A

N/A

N/A

N/A

et0mdcport

et0mdeport

N/A

N/A

N/A

N/A

et0phyaddr

et0phyaddr

N/A

N/A

N/A

N/A

et1macaddr

et1mac

0x54

N/A

N/A

N/A

N/A

et1mdcport

et1mdeport

N/A

N/A

N/A

N/A

et1phyaddr

et1phyaddr

N/A

N/A

N/A

N/A

il0macaddr

il0mac

0x48

0x4A

0x4C

0x52

0x8C

ledbh0

0x00FF

0x64

0x56

0x76

0x96

ledbh1

0xFF00

0x64

0x56

0x76

0x96

ledbh2

0x00FF

0x66

0x58

0x78

0x98

ledbh3

0xFF00

0x66

0x58

0x78

0x98

leddc

0x7C

0x5A

0x5A

0x9A

mcs2gpo0

0x14A

0x152

mcs2gpo1

0x14C

0x154

mcs2gpo2

0x14E

0x156

mcs2gpo3

0x150

0x158

mcs2gpo4

0x152

0x15A

mcs2gpo5

0x154

0x15C

mcs2gpo6

0x156

0x15E

mcs2gpo7

0x158

0x160

mcs5ghpo0

0x17A

0x182

mcs5ghpo1

0x17C

0x184

mcs5ghpo2

0x17E

0x186

mcs5ghpo3

0x180

0x188

mcs5ghpo4

0x182

0x18A

mcs5ghpo5

0x184

0x18C

mcs5ghpo6

0x186

0x18E

mcs5ghpo7

0x188

0x190

mcs5glpo0

0x16A

0x172

mcs5glpo1

0x16C

0x174

mcs5glpo2

0x16E

0x176

mcs5glpo3

0x170

0x178

mcs5glpo4

0x172

0x17A

mcs5glpo5

0x174

0x17C

mcs5glpo6

0x176

0x17E

mcs5glpo7

0x178

0x180

mcs5gpo0

0x15A

0x162

mcs5gpo1

0x15C

0x164

mcs5gpo2

0x15E

0x166

mcs5gpo3

0x160

0x168

mcs5gpo4

0x162

0x16A

mcs5gpo5