bcm-v4

[Specification

LP PHY Rev0 Baseband Init

  1. Clear bit 0x0800 in PHY Register 0x439

  2. Write 0 to PHY Registers 0x43A, 0x43B, 0x44C, and 0x4B0

  3. Set bit 0x4 in PHY Register 0x439

  4. MaskSet PHY Register 0x417 with mask 0xFF00 and set with 0x0078

  5. MaskSet PHY Register 0x420 with mask 0x83FF and set with 0x5800

  6. Write 0x0016 to PHY Register 0x470

  7. MaskSet PHY Register 0x436 with mask 0xFFF8 and set with 0x0004

  8. MaskSet PHY Register 0x425 with mask 0x00FF and set with 0x5400

  9. MaskSet PHY Register 0x423 with mask 0x00FF and set with 0x2400

  10. MaskSet PHY Register 0x424 with mask 0x00FF and set with 0x2100

  11. MaskSet PHY Register 0x425 with mask 0xFF00 and set with 0x0006

  12. Clear bit 0x0001 in PHY Register 0x4AE

  13. MaskSet PHY Register 0x420 with mask 0xFFE0 and set with 0x0005

  14. MaskSet PHY Register 0x420 with mask 0xFC1F and set with 0x0180

  15. MaskSet PHY Register 0x420 with mask 0x83FF and set with 0x3C00

  16. MaskSet PHY Register 0x427 with mask 0xFFF0 and set with 0x0005

  17. MaskSet PHY Register 0x431 with mask 0xFFC0 and set with 0x001A

  18. MaskSet PHY Register 0x432 with mask 0xFF00 and set with 0x00B3

  19. MaskSet PHY Register 0x432 with mask 0x00FF and set with 0xAD00

  20. If this is a 5G channel
    1. MaskSet PHY Register 0x434 with mask 0xFF00 and set with lpphy_rx_power_offset_5g

  21. Otherwise
    1. MaskSet PHY Register 0x434 with mask 0xFF00 and set with lpphy_rx_power_offset_2g

  22. If bit 0x800 is set in the boardflags AND (the current band is 5GHz OR bit 0x40000 is set in the board flags)
    1. Set the LDO voltage to 0x28 (unless there's a "parefldovoltage" board NVRAM value, in which case use that)
    2. set PMU LDO voltage "PA reference" to the LDO voltage value

    3. enable PMU PA ref LDO

    4. If the PHY revision is 0
      1. MaskSet PHY Register 0x4AC with mask FFCF and set with 0x0010

    5. Set delay to 60
  23. Otherwise
    1. disable PMU PA ref LDO

    2. MaskSet PHY Register 0x4AC with mask 0xFFCF and set with 0x0020

    3. Set delay to 100
  24. Write an LP table with ID 0x0B, offset 7, length 1, width 16, PHY width 16, and the data pointer to delay
  25. If this is a 5G channel
    1. Calculate lpphy_rssi_vf_5g | lpphy_rssi_vc_5g << 4 | lpphy_rssi_gs_5g << 10 | 0xA000 and write to PHY Register 0x43D

  26. Otherwise
    1. Calculate lpphy_rssi_vf_2g | lpphy_rssi_vc_2g << 4 | lpphy_rssi_gs_2g << 10 | 0xA000 and write to PHY Register 0x43D

  27. Set tmp to 0x2AA
  28. If bit 0x20000 is set in the board flags
    1. Set bit 0x0800 in tmp
  29. MaskSet PHY Register 0x43E with mask 0xF000 and set with tmp

  30. Set delay to 24
  31. Write an LP table with ID 0x0B, offset 1, length 1, width 16, PHY width 16, and the data 24
  32. If this is a 5G channel
    1. MaskSet PHY Register 0x4AE with mask FFF9 and set with (lpphy_bx_arch_5g << 1)

  33. Otherwise
    1. MaskSet PHY Register 0x4AE with mask FFF9 and set with (lpphy_bx_arch_2g << 1)

  34. If the PHY revision is 1 AND (boardflags & 0x00400000) is not zero)

    1. MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x000A

    2. MaskSet PHY Register 0x44E with mask 0x3F00 and set with 0x0900

    3. MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x000A

    4. MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0B00

    5. MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x000A

    6. MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0400

    7. MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x000A

    8. MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0B00

    9. MaskSet PHY Register 0x4C7 with mask 0xFFC0 and set with 0x000A

    10. MaskSet PHY Register 0x4C7 with mask 0xC0FF and set with 0x0900

    11. MaskSet PHY Register 0x4C8 with mask 0xFFC0 and set with 0x000A

    12. MaskSet PHY Register 0x4C8 with mask 0xC0FF and set with 0x0B00

    13. MaskSet PHY Register 0x4C9 with mask 0xFFC0 and set with 0x000A

    14. MaskSet PHY Register 0x4C9 with mask 0xC0FF and set with 0x0900

    15. MaskSet PHY Register 0x4CA with mask 0xFFC0 and set with 0x000A

    16. MaskSet PHY Register 0x4CA with mask 0xC0FF and set with 0x0B00

  35. Else if (the band type is 5G) OR (the board type is 0x048a) OR ((PHY revision is 1) AND (boardflags & 0x00000800) is set)

    1. MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x0001

    2. MaskSet PHY Register 0x44E with mask 0xC0FF and set with 0x0400

    3. MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x0001

    4. MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0500

    5. MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x0002

    6. MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0800

    7. MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x0002

    8. MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0A00

  36. Else if PHY revision is 1 AND (boardflags & 0x00000800) is set

    1. MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x0004

    2. MaskSet PHY Register 0x44E with mask 0xC0FF and set with 0x0800

    3. MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x0004

    4. MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0C00

    5. MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x0002

    6. MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0100

    7. MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x0002

    8. MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0300

  37. Otherwise
    1. MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x000A

    2. MaskSet PHY Register 0x44E with mask 0xC0FF and set with 0x0900

    3. MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x000A

    4. MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0B00

    5. MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x0006

    6. MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0500

    7. MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x0006

    8. MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0700

  38. If the PHY revision is 1 AND Bit 0x400000 is not set in the board fags
    1. Copy PHY Register 0x44E to PHY Register 0x4C7

    2. Copy PHY Register 0x44F to PHY Register 0x4C8

    3. Copy PHY Register 0x4BB to PHY Register 0x4C9

    4. Copy PHY Register 0x4BC to PHY Register 0x4CA

  39. If (boardflags & 0x00100000 is not zero) AND the chip ID is 0x5354 AND the chip package is 1

    1. Set bits 0x0006 in PHY Register 0x410

    2. Write 0x0005 to PHY Register 0x4BF

    3. Write 0xFFFF to PHY Register 0x4BE

    4. Call mhf with arguments ( 2, 0x0800, 0x0800, 1)

  40. If the current band is 2 GHz
    1. Set bit 0x8000 in PHY Register 0x448

    2. Set bit 0x0040 in PHY Register 0x410

    3. MaskSet PHY Register 0x416 with mask 0x00FF and set with 0xA400

    4. MaskSet PHY Register 0x410 with mask 0xF0FF and set with 0x0B00

    5. MaskSet PHY Register 0x030 with mask 0xFFF8 and set with 0x0007

    6. MaskSet PHY Register 0x42F with mask 0xFFF8 and set with 0x0003

    7. MaskSet PHY Register 0x42F with mask 0xFFC7 and set with 0x0020

    8. AND PHY Register 0x41A with mask 0x00FF

  41. Otherwise
    1. AND PHY Register 0x448 with mask 0x7FFF

    2. AND PHY Register 0x410 with mask 0xFFBF

  42. If the PHY revision is 1
    1. Read PHY Register 0x420, mask with 0x03E0 and right shift the result by 5

    2. OR the previous result with the value left shifted by 5 and write the result to PHY Register 0x4C3

    3. Read PHY Register 0x427, mask with 0x1F00 and right shift the result by 8

    4. OR the previous result with the value left shifted by 5 and write the result to PHY Register 0x4C4

    5. Read PHY Register 0x425 and mask with 0x00FF

    6. OR the previous result with the value left shifted by 8 and write the result to PHY Register 0x4C5


Exported/Archived from the wiki to HTML on 2016-10-27