LP PHY Rev0 Baseband Init
Clear bit 0x0800 in PHY Register 0x439
Write 0 to PHY Registers 0x43A, 0x43B, 0x44C, and 0x4B0
Set bit 0x4 in PHY Register 0x439
MaskSet PHY Register 0x417 with mask 0xFF00 and set with 0x0078
MaskSet PHY Register 0x420 with mask 0x83FF and set with 0x5800
Write 0x0016 to PHY Register 0x470
MaskSet PHY Register 0x436 with mask 0xFFF8 and set with 0x0004
MaskSet PHY Register 0x425 with mask 0x00FF and set with 0x5400
MaskSet PHY Register 0x423 with mask 0x00FF and set with 0x2400
MaskSet PHY Register 0x424 with mask 0x00FF and set with 0x2100
MaskSet PHY Register 0x425 with mask 0xFF00 and set with 0x0006
Clear bit 0x0001 in PHY Register 0x4AE
MaskSet PHY Register 0x420 with mask 0xFFE0 and set with 0x0005
MaskSet PHY Register 0x420 with mask 0xFC1F and set with 0x0180
MaskSet PHY Register 0x420 with mask 0x83FF and set with 0x3C00
MaskSet PHY Register 0x427 with mask 0xFFF0 and set with 0x0005
MaskSet PHY Register 0x431 with mask 0xFFC0 and set with 0x001A
MaskSet PHY Register 0x432 with mask 0xFF00 and set with 0x00B3
MaskSet PHY Register 0x432 with mask 0x00FF and set with 0xAD00
- If this is a 5G channel
MaskSet PHY Register 0x434 with mask 0xFF00 and set with lpphy_rx_power_offset_5g
- Otherwise
MaskSet PHY Register 0x434 with mask 0xFF00 and set with lpphy_rx_power_offset_2g
- If bit 0x800 is set in the boardflags AND (the current band is 5GHz OR bit 0x40000 is set in the board flags)
- Set the LDO voltage to 0x28 (unless there's a "parefldovoltage" board NVRAM value, in which case use that)
set PMU LDO voltage "PA reference" to the LDO voltage value
enable PMU PA ref LDO
- If the PHY revision is 0
MaskSet PHY Register 0x4AC with mask FFCF and set with 0x0010
- Set delay to 60
- Otherwise
disable PMU PA ref LDO
MaskSet PHY Register 0x4AC with mask 0xFFCF and set with 0x0020
- Set delay to 100
- Write an LP table with ID 0x0B, offset 7, length 1, width 16, PHY width 16, and the data pointer to delay
- If this is a 5G channel
Calculate lpphy_rssi_vf_5g | lpphy_rssi_vc_5g << 4 | lpphy_rssi_gs_5g << 10 | 0xA000 and write to PHY Register 0x43D
- Otherwise
Calculate lpphy_rssi_vf_2g | lpphy_rssi_vc_2g << 4 | lpphy_rssi_gs_2g << 10 | 0xA000 and write to PHY Register 0x43D
- Set tmp to 0x2AA
- If bit 0x20000 is set in the board flags
- Set bit 0x0800 in tmp
MaskSet PHY Register 0x43E with mask 0xF000 and set with tmp
- Set delay to 24
- Write an LP table with ID 0x0B, offset 1, length 1, width 16, PHY width 16, and the data 24
- If this is a 5G channel
MaskSet PHY Register 0x4AE with mask FFF9 and set with (lpphy_bx_arch_5g << 1)
- Otherwise
MaskSet PHY Register 0x4AE with mask FFF9 and set with (lpphy_bx_arch_2g << 1)
If the PHY revision is 1 AND (boardflags & 0x00400000) is not zero)
MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x44E with mask 0x3F00 and set with 0x0900
MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0B00
MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0400
MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0B00
MaskSet PHY Register 0x4C7 with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x4C7 with mask 0xC0FF and set with 0x0900
MaskSet PHY Register 0x4C8 with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x4C8 with mask 0xC0FF and set with 0x0B00
MaskSet PHY Register 0x4C9 with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x4C9 with mask 0xC0FF and set with 0x0900
MaskSet PHY Register 0x4CA with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x4CA with mask 0xC0FF and set with 0x0B00
Else if (the band type is 5G) OR (the board type is 0x048a) OR ((PHY revision is 1) AND (boardflags & 0x00000800) is set)
MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x0001
MaskSet PHY Register 0x44E with mask 0xC0FF and set with 0x0400
MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x0001
MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0500
MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x0002
MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0800
MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x0002
MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0A00
Else if PHY revision is 1 AND (boardflags & 0x00000800) is set
MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x0004
MaskSet PHY Register 0x44E with mask 0xC0FF and set with 0x0800
MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x0004
MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0C00
MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x0002
MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0100
MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x0002
MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0300
- Otherwise
MaskSet PHY Register 0x44E with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x44E with mask 0xC0FF and set with 0x0900
MaskSet PHY Register 0x44F with mask 0xFFC0 and set with 0x000A
MaskSet PHY Register 0x44F with mask 0xC0FF and set with 0x0B00
MaskSet PHY Register 0x4BB with mask 0xFFC0 and set with 0x0006
MaskSet PHY Register 0x4BB with mask 0xC0FF and set with 0x0500
MaskSet PHY Register 0x4BC with mask 0xFFC0 and set with 0x0006
MaskSet PHY Register 0x4BC with mask 0xC0FF and set with 0x0700
- If the PHY revision is 1 AND Bit 0x400000 is not set in the board fags
Copy PHY Register 0x44E to PHY Register 0x4C7
Copy PHY Register 0x44F to PHY Register 0x4C8
Copy PHY Register 0x4BB to PHY Register 0x4C9
Copy PHY Register 0x4BC to PHY Register 0x4CA
If (boardflags & 0x00100000 is not zero) AND the chip ID is 0x5354 AND the chip package is 1
Set bits 0x0006 in PHY Register 0x410
Write 0x0005 to PHY Register 0x4BF
Write 0xFFFF to PHY Register 0x4BE
Call mhf with arguments ( 2, 0x0800, 0x0800, 1)
- If the current band is 2 GHz
Set bit 0x8000 in PHY Register 0x448
Set bit 0x0040 in PHY Register 0x410
MaskSet PHY Register 0x416 with mask 0x00FF and set with 0xA400
MaskSet PHY Register 0x410 with mask 0xF0FF and set with 0x0B00
MaskSet PHY Register 0x030 with mask 0xFFF8 and set with 0x0007
MaskSet PHY Register 0x42F with mask 0xFFF8 and set with 0x0003
MaskSet PHY Register 0x42F with mask 0xFFC7 and set with 0x0020
AND PHY Register 0x41A with mask 0x00FF
- Otherwise
AND PHY Register 0x448 with mask 0x7FFF
AND PHY Register 0x410 with mask 0xFFBF
- If the PHY revision is 1
Read PHY Register 0x420, mask with 0x03E0 and right shift the result by 5
OR the previous result with the value left shifted by 5 and write the result to PHY Register 0x4C3
Read PHY Register 0x427, mask with 0x1F00 and right shift the result by 8
OR the previous result with the value left shifted by 5 and write the result to PHY Register 0x4C4
Read PHY Register 0x425 and mask with 0x00FF
OR the previous result with the value left shifted by 8 and write the result to PHY Register 0x4C5