bcm-v4

[Specification

PCI Core

The Backplane always contains one core responsible for interacting with the computer. In most cards, it is connected via the PCI core. This core has a Core ID of 0x804.

Registers

Offset

Size

Meaning

Notes

0x0000

4

PCI Control

0x0010

4

PCI Arbiter Control

0x0020

4

Interrupt Status

0x0024

4

Interrupt Mask

0x0028

4

Backplane to PCI Mailbox

0x0050

4

Backplane Broadcast Address

0x0054

4

Backplane Broadcast Data

0x0060

4

GPIO In

Core Revision 2 or greater

0x0064

4

GPIO Out

Core Revision 2 or greater

0x0068

4

GPIO Enable

Core Revision 2 or greater

0x006C

4

GPIO Control

Core Revision 2 or greater

0x0100

4

Backplane to PCI Translation 0

0x0104

4

Backplane to PCI Translation 1

0x0108

4

Backplane to PCI Translation 2

PCI Control

Offset

Meaning

0x00000001

Drive PCI_RESET to pin

0x00000002

Reset value driven to pin

0x00000004

Drive clock as gated by bit 0x00000008 out to pin

0x00000008

Gate for clock driven out to pin

Backplane to PCI Translation

Mask

Meaning

Notes

0x00000003

Destination

0x00000004

Prefetch Enable

0x00000008

Burst Enable

0x00000030

Read Command

Core Revision 11 or higher

Destinations

0

Memory

1

IO

2

CFG 0

3

CFG 1

Read Commands

0

Memory Read

1

Memory Read Line

2

Memory Read Multiple

Broadcasting Data Over the Bus

First write the address to the broadcast address register, then the data to the broadcast data register.


Exported/Archived from the wiki to HTML on 2016-10-27