PCI-E - bcm-specs

Contents

PCI-E Core
Registers
Reading and writing PCI-E Configuration Space or PCI-E Registers
PCI-E Configuration Space Registers
PCI-E Registers
MDIO Access

PCI-E Core

The Backplane always contains one core responsible for interacting with the computer. In the newer PCI-E cards, it is connected via the PCI-E Core. This core has a Core ID of 0x820.

Registers

Offset	Size	Meaning
`0x000C`	4	BIST Status
`0x0028`	4	Backplane to PCI-E Mailbox
`0x0100`	4	Backplane to PCI-E Translation 0 (sbtopcie0)
`0x0104`	4	Backplane to PCI-E Translation 1 (sbtopcie1)
`0x0108`	4	Backplane to PCI-E Translation 2 (sbtopcie2)
`0x0120`	4	PCI-E Configuration Space: Address
`0x0124`	4	PCI-E Configuration Space: Data
`0x0128`	4	MDIO Access: Control
`0x012C`	4	MDIO Access: Data
`0x0130`	4	PCI-E PHY/DLLP/TLP Register Access: Address
`0x0134`	4	PCI-E PHY/DLLP/TLP Register Access: Data

Reading and writing PCI-E Configuration Space or PCI-E Registers

First, write the register offset to the control register (0x120 for PCI-E Configuration Registers or 0x130 for PCI-E Registers), then either read or write the the associated data register.

PCI-E Configuration Space Registers

PCI-E Registers

Offset	Size	Usage
TLP Diagnostic Registers
`0x0000`	4	Configuration Register
`0x0004`	4	TLP Workarounds Register
`0x0010`	4	Write DMA Upper Address
`0x0014`	4	Write DMA Lower Address
`0x0018`	4	Write DMA Request Lenth / Byte Encoding
`0x001C`	4	Read DMA Upper Address
`0x0020`	4	Read DMA Lower Address
`0x0024`	4	Read DMA Request Length
`0x0028`	4	MSI DMA Upper Address
`0x002C`	4	MSI DMA Lower Address
`0x0030`	4	MSI DMA Request Length
`0x0034`	4	Slave Request Length
`0x0038`	4	Flow Control Inputs
`0x003C`	4	TX State Machine and Gated Request
`0x0040`	4	Address ACK, Transfer Count and ARB Length
`0x0044`	4	DMA Completion Header 0
`0x0048`	4	DMA Completion Header 1
`0x004C`	4	DMA Completion Header 2
`0x0050`	4	DMA Completion Misc 0
`0x0054`	4	DMA Completion Misc 1
`0x0058`	4	DMA Completion Misc 2
`0x005C`	4	Split Controller Request Length
`0x0060`	4	Splig Controller Misc 0
`0x0064`	4	Splig Controller Misc 1
`0x0068`	4	Bus / Device Function
`0x006C`	4	Reset Counter
`0x0070`	4	Retry Buffer Value
`0x0074`	4	Target Debug Register 1
`0x0078`	4	Target Debug Register 2
`0x007C`	4	Target Debug Register 3
`0x0080`	4	Target Debug Register 4
DLLP Diagnostic Registers
`0x0100`	4	Link Control Register
`0x0104`	4	Link Status
`0x0108`	4	Link Attention
`0x010C`	4	Link Attention Mask
`0x0110`	4	Next TX Sequence Number
`0x0114`	4	ACK'd TX Sequence Number
`0x0118`	4	Purged TX Sequence Number
`0x011C`	4	RX Sequence Number
`0x0120`	4	Link Replay
`0x0124`	4	Link ACK Timeout
`0x0128`	4	Power Management Threshold
`0x012C`	4	Retry Buffer Write Pointer
`0x0130`	4	Retry Buffer Read Pointer
`0x0134`	4	Retry Buffer Purged Pointer
`0x0138`	4	Retry Buffer Read / Write
`0x013C`	4	Error Count Threshold
`0x0140`	4	TLP Error Counter
`0x0144`	4	Error Counter
`0x0148`	4	NAK Received Counter
`0x014C`	4	Test Register
`0x0150`	4	Packet BIST
PHY Diagnostic Registers
`0x0200`	4	Mode
`0x0204`	4	Status
`0x0208`	4	LTSSM Control
`0x020C`	4	Link Training Link Number
`0x0210`	4	Link Training Lane Number
`0x0214`	4	Link Training N FTS
`0x0218`	4	Attention
`0x021C`	4	Attention Mask
`0x0220`	4	RX Error Counter
`0x0224`	4	RX Framing Error Counter
`0x0228`	4	RX Error Threshold
`0x022C`	4	Test Control Register
`0x0230`	4	SERDES Control Override
`0x0234`	4	Timing Parameters Override
`0x0238`	4	RX/TX State Machine Diag
`0x023C`	4	LTSSM State Machine Diag

MDIO Access

MDIO Control Register Usage

Bitmask	Usage
`0x007F`	MDIO Clock Divsor
`0x0080`	Enable/Disable Preamble Sequence
`0x0100`	MDIO Transaction Complete

MDIO SERDES Devices

Address	Device
`0x1F`	SERDES RX Device

SERDES RX Device Registers

Offset	Usage
2	RX Timer
6	CDR
7	CDR BW

Write to MDIO Slaves

Write 0x82 (Enable Preamble Sequence bitwise OR'd with a divisor value of 2) to the MDIO Control Register
Prepare the MDIO data packet with the Start of Transaction bit set, the Write Transaction bit set and the Turnaround bit set, finally, fill in the addresses and data as needed
Write the MDIO data packet to the MDIO Data Register
Delay for 10 uSec
Check every 1 mSec for 10 mSec to see if the MDIO Transaction Complete bit is set in the MDIO Control Register
Once the transaction is completed or fails, write 0 to the MDIO Control register

MDIO Data Packet Format

Mask	Function
`0x40000000`	Start of Transaction
`0x20000000`	Read Transaction
`0x10000000`	Write Transaction
`0x0FC00000`	Device Address
`0x003C0000`	Register
`0x00020000`	Turnaround
`0x0000FFFF`	Data