bcm-v4

[Specification

Backplane Basics

The Sonics Silicon Backplane functions as a switch that can switch between active "cores" to enable or disable functionality. When a core is switched to, its parameters(registers) can be accessed through mapped memory.

PCI Configuration Space Registers

/!\ Only used common PCI Registers are shown here

Offset

Size

Function

Notes

Common PCI Registers

0x06

2

PCI Status

0x08

1

PCI Revision ID

Chip Revision

0x2C

2

PCI Subsystem Vendor ID

Board Vendor

0x2E

2

PCI Subsystem ID

Board Type

Broadcom Specific Registers

0x80

4

Backplane Address Space 0

Maps a Core into Mapped Memory

0x84

4

Backplane Address Space 1

Maps a Core into Mapped Memory

0x88

4

SPROM Control

0x8C

4

Backplane Address 1 Burst control

0x90

4

PCI Interrupts

0x94

4

PCI Interrupt Control Register/Interrupt Mask

PCI Revision 6 or greater only

0x98

4

Backplane Interrupts

0xB0

4

PCI Configuration Space GPIO Input

PCI Revision 3 or greater only

0xB4

4

PCI Configuration Space GPIO Output

PCI Revision 3 or greater only

0xB8

4

PCI Configuration Space GPIO Output Enable/Disable

PCI Revision 3 or greater only

Board Vendor

Actually PCI Vendor IDs

ID

Vendor

0x14E4

Broadcom

0x1028

Dell

0x0E11

HP

Board Type

Reference Board Types

Code

Type

0x0418

BCM94306MP

0x0421

BCM4309G

0x0417

BCM4306CB

0x040C

BCM4309MP

0x044A

MP4318

0x0416

BU4306

0x040A

BU4309

Backplane Address Space 0

This register controls which backplane address is currently mapped into the mapped memory. Each core uses 0x1000 bytes (4K) for registers, so when setting the mapped core, take the Core Index multiplied by 0x1000 (the size of the core registers) and add that to the base value of 0x18000000. Note that mapping may not succeed on the first attempt, so the proper method of mapping is to write the register, then read back the value until it is actually set to the desired value (max 10 times). To find which core is mapped, read this register and do the above calculation in reverse.

Backplane Registers

The Backplane's registers are the Common Registers in the attached core.

Offset

Size

Function

Notes

0x0EA8

4

IM Error Log A

Backplane Revision >= 2.3 Only

0x0EB0

4

IM Error Log

Backplane Revision >= 2.3 Only

0x0ED8

4

TM Port Connection ID 0

Backplane Revision >= 2.3 Only

0x0EF8

4

TM Port Lock 0

Backplane Revision >= 2.3 Only

0x0F08

4

IPS Flag

0x0F18

4

TPS Flag

0x0F48

4

TM Error Log A

Backplane Revision >= 2.3 Only

0x0F50

4

TM Error Log

Backplane Revision >= 2.3 Only

0x0F60

4

Address Match 3

0x0F68

4

Address Match 2

0x0F70

4

Address Match 1

0x0F90

4

IM State

0x0F94

4

Interrupt Vector

0x0F98

4

TM State Low

0x0F9C

4

TM State High

0x0FA0

4

BWA0

0x0FA8

4

IM Config Low

0x0FAC

4

IM Config High

0x0FB0

4

Address Match 0

0x0FB8

4

TM Config Low

0x0FBC

4

TM Config High

0x0FC0

4

B Config

0x0FC8

4

B State

0x0FD8

4

ACTCNFG

0x0FE8

4

FLAGST

0x0FF8

4

Core ID Low

0x0FFC

4

Core ID High

0x1000

-

SPROM Shadow Area

IM State

Mask

Function

Notes

0x0000000F

Pipe Count

0x00000030

Arbitration Policy

0x00020000

In Band Error

0x00040000

Timeout

0x01800000

Busy

Backplane Revision >= 2.3 Only

0x02000000

Reject

Backplane Revision >= 2.3 Only

Core ID Low

Mask

Function

Notes

0x00000003

Config Space

0x00000038

Address Ranges Supported

0x00000040

Sync

0x00000080

Initiator

0x00000F00

Minimum Backplane Latency

0x0000F000

Maximum Backplane Latency

0x00010000

This Initiator is First

0x000C0000

Cycle Counter Width

0x00F00000

Target Ports

0x0F000000

Initiator Ports

0xF0000000

Sonics Backplane Revision Code

Backplane Revision Code

Revision Code

Sonics Revision

0

<= Version 2.2

1

Version 2.3

4

Found in BCM4328

7

Found in BCM4311 rev 2

TM State Low

Mask

Function

0x00000001

Reset

0x00000006

Reject

0x00010000

Clock Enable

0x00020000

Force Gated Clocks On

0x3FFC0000

Core Specific Flags

0x40000000

PME Enable

0x80000000

BIST Enable

Reject

The "Reject" bit changed between revisions, use the correct value for the current Backplane Revision

Bit

Revision

0x00000002

Backplane Revision 2.2

0x00000004

Backplane Revision 2.3

TM State High

Mask

Function

Notes

0x00000001

S Error

0x00000002

Interrupt

0x00000004

Busy

0x00000020

Timeout

Backplane Revision >= 2.3 Only

0x1FFF0000

Core Specific Flags

0x10000000

Supports 64 Bit DMA

0x20000000

Gated Clock Request

0x40000000

BIST Failed

0x80000000

BIST Done

Determining Bus Type

In this spec (for now) we only support PCI and PCI-E busses. If someone can find a device that doesn't have a PCI or PCI-E interface, please let us know.

Some Silicon Backplane cores present themselves as PCI Cores. To detect this, try reading from the SPROM PCI Config Register. If the value is 0xFFFFFFFF, this is actually a Silicon Backplane Bus.

Attaching

  1. Turn on the Clock Crystal

Detaching

Clock Control

Determine the Chip ID and the Number of Cores

If present, you can get these values from the ChipCommon core. In the event no ChipCommon core is present, use the following table.

Chip ID

Number of Cores

0x4710, 0x4610, 0x4704

9

0x4402

3

0x4307, 0x4301

5

0x4310

8

0x4306

6

0x5365

7

Resetting and Enabling a Core

  1. Disable the Core to account for a core in a random state
  2. Force the clocks on throughout the core, and reset it:

    1. Write the "Force Gated Clocks On", "Clock Enable",and "Reset" bits along with any device specific flags requested, to the TM State Low register (unset the rest)

    2. Perform a dummy read on the TM State Low register

    3. Delay 1uS
  3. If the S Error bit is set in the TM State High register

    1. Clear all of the bits in TM State High (write 0)

  4. Unset the "In Band Error" or "Timeout" bits if the IM State register has them set

  5. Clear the reset and wait for the core to see the clear:

    1. Write the "Force Gated Clocks On", "Clock Enable" bits, along with any device specific flags requested, to the TM State Low register (unset the rest)

    2. Perform a dummy read on the TM State Low register

    3. Delay 1uS
  6. We no longer need to force the clocks, but leave the clock enabled:

    1. Write the "Clock Enable" bit along with any device specific flags requested to the TM State Low register (unset the rest)

    2. Delay 1uS

Disabling a Core - u32 flags is argument

  1. If TM_STATE_LOW & 1 is not zero

    1. Return
  2. If TM_STATE_LOW & (1 << 16) is not zero

    1. Set bit 2 in TM_STATE_LOW
    2. Do dummy read of TM_STATE_LOW
    3. Delay 1 usec
    4. spinwait for bit 4 of TM_STATE_HIGH to be unset
    5. If bit 0x80 in SSB_IDLOW is set
      1. Set bit 0x2000000 in IM_STATE
      2. Do dummy read of IM_STATE
      3. Delay 1 usec
      4. Spinwait for IM_STATE & 0x1800000 to be zero

    6. Write (flags | 3) << 16 | 3 to TM_STATE_LOW

    7. Do dummy read of TM_STATE_LOW
    8. Delay 10 usec
    9. If bit 0x80 in CORE_ID_LOW is set
      1. Clear bit 0x2000000 in IM_STATE
  3. Write (flags << 16) | 3 to TM_STATE_LOW

  4. Delay 1usec

Check if a Core is Enabled

Activate a Core


Exported/Archived from the wiki to HTML on 2016-10-27