SSB PMU Recalibrate

1. If the chip ID is not 0x4325
   1. Return
2. Save the current core index
3. Switch to the chipcommon core
4. Write 1 to SSB_CHIPCO_CHIPCTL_ADDR
5. Clear bit 0x04 in SSB_CHIPCO_CHIPCTL_DATA
6. Read SSB_CHIPCO_CHIPSTAT and mask with 0x08 and right shift by 3
7. If the result is not zero
   1. Set tmp to 6
8. Otherwise
   1. Set tmp to 0
9. Set bit 0x04 in SSB_CHIPCO_CHIPCTL_DATA
10. Spin wait for SSB_CHIPCO_CHIPSTAT ANDed with 0x08 to be zero. Test every 10 usec and loop for a maximum of 1 million times (?? - very long)
11. Error if the loop times out
12. If tmp is zero
    1. Set tmp to SSB_CHIPCO_CHIPSTAT right shifted by 5 and ANDed with 0x0F
13. Write 0 to SSB_CHIPCO_REGCTL_ADDR

14. MaskSet SSB_CHIPCO_REGCTL_DATA using mask ~(0x07 << 29) and set with (tmp & 0x07) << 29

15. Write 1 to SSB_CHIPCO_REGCTL_ADDR

16. MaskSet SSB_CHIPCO_REGCTL_DATA using mask ~0x01 and set with (tmp >> 3) ANDed with 0x01

17. Write 0 to SSB_CHIPCO_CHIPCTL_ADDR

18. MaskSet SSB_CHIPCO_CHIPCTL_DATA with mask ~(0x03 << 30) and set with (tmp & 0x03) << 30

19. Write 1 to SSB_CHIPCO_CHIPCTL_ADDR

20. MaskSet SSB_CHIPCO_CHIPCTL_DATA with mask ~0x03 and set with (tmp >> 2) & 0x03

21. Write 0 to SSB_CHIPCO_CHIPCTL_ADDR

22. Set bit 0x01 << 29 in SSB_CHIPCO_CHIPCTL_DATA

23. Write 1 to SSB_CHIPCO_CHIPCTL_ADDR
24. Clear bit 0x04 in SSB_CHIPCO_CHIPCTL_DATA
25. Restore original core