802.11/Radio/2055/Init

Contents

Pre Init
Init
1. Register Table
Post Init

Pre Init

AND PHY Register 0x78 with 0xFFBF
OR PHY Register 0x78 with 0x480
OR PHY Register 0x78 with 0x40

Init

The init routine simply writes the correct Radio Register value to the Radio Register in the Offset column. If the current channel is in the 5GHz band, use the 5GHz value. If the current channel is in the 2.4GHz band, use the 2.4GHz value. If the value does not require setting, you do not have to write that value to the Radio Register. For N PHYs with Revision less than 3 that are connected via PCI bus, the MAC Control register should be read after every 4 writes.

If the band cannot be determined (on init or otherwise), write all of the 2.4GHz Radio Register values, even if it's not required.

Register Table

This is a table of the default Radio Register values

Offset	5GHz Value	2.4GHz Value	Requires Setting (5 GHz)	Requires Setting (2.4 GHz)
0x02	0x80	0x80	0	0
0x03	0	0	0	0
0x04	0x27	0x27	0	0
0x05	0	0	0	0
0x06	0x27	0x27	0	0
0x07	0x7f	0x7f	1	1
0x08	0x7	0x7	1	1
0x09	0x7f	0x7f	1	1
0x0A	0x7	0x7	1	1
0x0B	0x15	0x15	0	0
0x0C	0x15	0x15	0	0
0x0D	0x4f	0x4f	1	1
0x0E	0x5	0x5	1	1
0x0F	0x4f	0x4f	1	1
0x10	0x5	0x5	1	1
0x11	0xd0	0xd0	0	0
0x12	0x2	0x2	0	0
0x13	0	0	0	0
0x14	0x40	0x40	0	0
0x15	0	0	0	0
0x16	0	0	0	0
0x17	0	0	0	0
0x18	0	0	0	0
0x19	0	0	0	0
0x1A	0	0	0	0
0x1B	0	0	0	0
0x1C	0	0	0	0
0x1D	0xc0	0xc0	0	0
0x1E	0xff	0xff	0	0
0x1F	0xc0	0xc0	0	0
0x20	0xff	0xff	0	0
0x21	0xc0	0xc0	0	0
0x22	0	0	0	0
0x23	0x2c	0x2c	0	0
0x24	0	0	0	0
0x25	0	0	0	0
0x26	0	0	0	0
0x27	0	0	0	0
0x28	0	0	0	0
0x29	0	0	0	0
0x2A	0	0	0	0
0x2B	0	0	0	0
0x2C	0	0	0	0
0x2D	0xa4	0xa4	0	0
0x2E	0x38	0x38	0	0
0x2F	0	0	0	0
0x30	0x4	0x4	1	1
0x31	0	0	0	0
0x32	0xa	0xa	0	0
0x33	0x87	0x87	0	0
0x34	0x9	0x9	0	0
0x35	0x70	0x70	0	0
0x36	0x11	0x11	0	0
0x37	0x18	0x18	1	1
0x38	0x6	0x6	0	0
0x39	0x4	0x4	1	1
0x3A	0x6	0x6	0	0
0x3B	0x9e	0x9e	0	0
0x3C	0x9	0x9	0	0
0x3D	0xc8	0xc8	1	1
0x3E	0x88	0x88	0	0
0x3F	0	0	0	0
0x40	0	0	0	0
0x41	0	0	0	0
0x42	0x1	0x1	0	0
0x43	0x2	0x2	0	0
0x44	0x96	0x96	0	0
0x45	0x3e	0x3e	0	0
0x46	0x3e	0x3e	0	0
0x47	0x13	0x13	0	0
0x48	0x2	0x2	0	0
0x49	0x15	0x15	0	0
0x4A	0x7	0x7	0	0
0x4B	0	0	0	0
0x4C	0	0	0	0
0x4D	0	0	0	0
0x4E	0	0	0	0
0x4F	0	0	0	0
0x50	0x8	0x8	0	0
0x51	0x8	0x8	0	0
0x52	0x6	0x6	0	0
0x53	0x84	0x84	1	1
0x54	0xc3	0xc3	0	0
0x55	0x8f	0x8f	0	0
0x56	0xff	0xff	0	0
0x57	0xff	0xff	0	0
0x58	0x88	0x88	0	0
0x59	0x88	0x88	0	0
0x5A	0	0	0	0
0x5B	0xcc	0xcc	0	0
0x5C	0x6	0x6	0	0
0x5D	0x80	0x80	0	0
0x5E	0x80	0x80	0	0
0x5F	0xf8	0xf8	0	0
0x60	0x88	0x88	0	0
0x61	0x88	0x88	0	0
0x62	0x88	0x8	1	1
0x63	0x88	0x88	0	0
0x64	0	0	0	0
0x65	0x1	0x1	1	1
0x66	0x8a	0x8a	0	0
0x67	0x8	0x8	0	0
0x68	0x83	0x83	0	0
0x69	0x6	0x6	0	0
0x6A	0xa0	0xa0	0	0
0x6B	0xa	0xa	0	0
0x6C	0x87	0x87	1	1
0x6D	0x2a	0x2a	0	0
0x6E	0x2a	0x2a	0	0
0x6F	0x2a	0x2a	0	0
0x70	0x2a	0x2a	0	0
0x71	0x18	0x18	0	0
0x72	0x6a	0x6a	1	1
0x73	0xab	0xab	1	1
0x74	0x13	0x13	1	1
0x75	0xc1	0xc1	1	1
0x76	0xaa	0xaa	1	1
0x77	0x87	0x87	1	1
0x78	0	0	0	0
0x79	0x6	0x6	0	0
0x7A	0x7	0x7	0	0
0x7B	0x7	0x7	0	0
0x7C	0x15	0x15	0	0
0x7D	0x55	0x55	0	0
0x7E	0x97	0x97	1	1
0x7F	0x8	0x8	0	0
0x80	0x14	0x14	1	1
0x81	0x33	0x33	0	0
0x82	0x88	0x88	0	0
0x83	0x6	0x6	0	0
0x84	0x3	0x3	1	1
0x85	0xa	0xa	0	0
0x86	0x3	0x3	1	1
0x87	0x2a	0x2a	0	0
0x88	0xa4	0xa4	0	0
0x89	0x18	0x18	0	0
0x8A	0x28	0x28	0	0
0x8B	0	0	0	0
0x8C	0x4a	0x4a	0	0
0x8D	0	0	0	0
0x8E	0xf8	0xf8	0	0
0x8F	0x88	0x88	0	0
0x90	0x88	0x88	0	0
0x91	0x88	0x8	1	1
0x92	0x88	0x88	0	0
0x93	0	0	0	0
0x94	0x1	0x1	1	1
0x95	0x8a	0x8a	0	0
0x96	0x8	0x8	0	0
0x97	0x83	0x83	0	0
0x98	0x6	0x6	0	0
0x99	0xa0	0xa0	0	0
0x9A	0xa	0xa	0	0
0x9B	0x87	0x87	1	1
0x9C	0x2a	0x2a	0	0
0x9D	0x2a	0x2a	0	0
0x9E	0x2a	0x2a	0	0
0x9F	0x2a	0x2a	0	0
0xA0	0x18	0x18	0	0
0xA1	0x6a	0x6a	1	1
0xA2	0xab	0xab	1	1
0xA3	0x13	0x13	1	1
0xA4	0xc1	0xc1	1	1
0xA5	0xaa	0xaa	1	1
0xA6	0x87	0x87	1	1
0xA7	0	0	0	0
0xA8	0x6	0x6	0	0
0xA9	0x7	0x7	0	0
0xAA	0x7	0x7	0	0
0xAB	0x15	0x15	0	0
0xAC	0x55	0x55	0	0
0xAD	0x97	0x97	1	1
0xAE	0x8	0x8	0	0
0xAF	0x14	0x14	1	1
0xB0	0x33	0x33	0	0
0xB1	0x88	0x88	0	0
0xB2	0x6	0x6	0	0
0xB3	0x3	0x3	1	1
0xB4	0xa	0xa	0	0
0xB5	0x3	0x3	1	1
0xB6	0x2a	0x2a	0	0
0xB7	0xa4	0xa4	0	0
0xB8	0x18	0x18	0	0
0xB9	0x28	0x28	0	0
0xBA	0	0	0	0
0xBB	0x4a	0x4a	0	0
0xBC	0	0	0	0
0xBD	0x71	0x71	0	0
0xBE	0x72	0x72	0	0
0xBF	0x73	0x73	0	0
0xC0	0x74	0x74	0	0
0xC1	0x75	0x75	0	0
0xC2	0x76	0x76	0	0
0xC3	0x77	0x77	0	0
0xC4	0x78	0x78	0	0
0xC5	0x79	0x79	0	0
0xC6	0x7a	0x7a	0	0
0xC7	0	0	0	0
0xC8	0	0	0	0
0xC9	0	0	0	0
0xCA	0	0	0	0
0xCB	0	0	0	0
0xCC	0	0	0	0
0xCD	0	0	0	0
0xCE	0x6	0x6	0	0
0xCF	0	0	0	0
0xD0	0	0	0	0
0xD1	0x18	0x18	0	0
0xD2	0x88	0x88	0	0
0xD3	0	0	0	0
0xD4	0	0	0	0
0xD5	0	0	0	0
0xD6	0	0	0	0
0xD7	0	0	0	0
0xD8	0	0	0	0
0xD9	0	0	0	0
0xDA	0x6	0x6	0	0
0xDB	0	0	0	0
0xDC	0	0	0	0
0xDD	0x18	0x18	0	0
0xDE	0x88	0x88	0	0
0xDF	0	0	0	0
0xE0	0	0	0	0
0xE1	0	0	0	0
0xE2	0	0	0	0

Post Init

AND Radio Register 0x11 with 0xFFF3
If {(the SROM Revision is less than 4) and [(the board vendor isn't 0x14E4) and (the board type is 0x46D) and (the board revision >= 0x41)]} or [(the SROM Revision is >= 4) and (Bit 0x1 in Boardflags2 isn't set)]
1. AND Radio Register 0x77 with 0x7F
2. AND Radio Register 0xA6 with 0x7F
MaskSet Radio Register 0x23 with mask 0xFFC0 and set 0x2C
Write 0x3C to Radio Register 0x24
AND Radio Register 0x24 with 0xFFBE
OR Radio Register 0x29 with 0x80
OR Radio Register 0x24 with 0x1
Delay 1000uSec
OR Radio Register 0x24 with 0x40
Wait for up to 2000 us, checking every 10uSec for Radio Register 0x26 to have bit 0x80 set
AND Radio Register 0x29 with 0xFF7F
Set the channel to the desired channel
Write 0x9 to Radio Register 0x6B
Write 0x9 to Radio Register 0x9A
Write 0x83 to Radio Register 0x6C
Write 0x83 to Radio Register 0x9B
MaskSet Radio Register 0xCD with mask 0xFFF8 and set 0x6
MaskSet Radio Register 0xD9 with mask 0xFFF8 and set 0x6
If nphy_gain_boost is zero
1. OR Radio Register 0x66 with 0x2
2. OR Radio Register 0x95 with 0x2
Otherwise
1. AND Radio Register 0x66 with 0xFFFD
2. AND Radio Register 0x95 with 0xFFFD
Delay 2 usec