bcm-v4

[Specification

General

There are 6 or 8 PIO queues, depending on the 802.11 core revision (see registers for the layout).

In addition to the differences in location, there are also two different methods of using PIO depending on the 802.11 core revision. If the revision is < 8, use the 2 byte method. If the revision is >= 8, use the 4 byte method.

2 Byte PIO Queue Registers

TX Channel

Offset

Size

Description

0x00

2

TX Control

0x02

2

TX Data (Endianness is affected by the "Big Endian" bit in the MAC Control register)

0x04

2

Internal PIO TX queue buffer size

0x06

2

Unused

TX Control Register

Mask

Function

0x0001

Write lower 8 bits

0x0002

Write upper 8 bits

0x0004

End of frame

0x0008

Frame Ready

0x0020

Flush Request

0x0040

Flush Pending

0x0080

Suspend Request

0x0100

Queue Suspended

0xFC00

Committed Count

RX Channel

0x00

2

RX Control

0x02

2

RX Data (Endianness is affected by the "Big Endian" bit in the MAC Control register)

0x04

2

Unused

0x06

2

Unused

RX Control Register

Mask

Function

0x0001

Frame Ready

0x0002

Data Ready

4 Byte PIO Queue Registers

TX/RX Channels

Offset

Size

Description

0x00

4

Control

0x04

4

Data (Endianness is affected by the "Big Endian" bit in the MAC Control register)

TX Control Register

Mask

Function

0x00000001

Write bits 0-7

0x00000002

Write bits 8-15

0x00000004

Write bits 16-23

0x00000008

Write bits 24-31

0x00000010

End of frame

0x00000080

Frame Ready

0x00000100

Suspend Request

0x00000200

Queue Suspended

0x00000400

Flush Request

0x00000800

Flush Pending

RX Control Register

Mask

Function

0x00000001

Frame Ready

0x00000002

Data Ready

Working With PIO Queues

PIO Queue Usage

PIO Queue usage is exactly as DMA usage, all queues for sending, queue 1 for receiving and queue 4 for receiving transmit status notifications on cores with revision < 3.

Initialization

  1. Setup the Packet Queues (Software linked lists really)
  2. If the 802.11 Core Revision is less than 3, bitwise OR 0x100 to the Chip Interrupt Mask

Resume the Transfer PIO Queue

  1. Clear bit 0x80 of the Transfer Control Register of the desired queue
  2. Calculate the PowerSavingControlBits

Suspend the Transfer PIO Queue

  1. Set the PowerSavingControlBits bit 26 and calculate bit 25

  2. Mask the Transfer Control Register of the desired queue with 0x80

Sending data to the 802.11 Core (Transmitting)

Buffering information

The PIO queues need to buffer the data that is to be transmitted. you need to make sure to not ever have more bytes outstanding than the internal buffer size (PIO TX Register 0x04) - 80 (no idea why -80, but it is like that, maybe some chip-internal accounting overhead and the register actually notes the complete memory that's available?). Additionally, you can only have at most 31 (32?) packets in the chip-internal buffer of a queue at a time. This means you need to account for the packets and bytes that are currently in the chip-internal PIO queues and need to assume they are in the queue until you get a transmit status notification. Note that if the PIO TX Queue Control register has the Suspend Queue bit set, you should also not buffer any more data for transmission.

Transmitting

  1. When starting a frame, write the "Frame Ready" bit to the "TX Control" register of the queue you want to send with.
  2. Set the "Write" bits in the "TX Control" register so that the bytes that will be written are accounted for
  3. The data can now be written to the "TX Data" register
  4. Repeat this process for each 16/32 bit value to send
  5. If there are an odd number of bytes to send, put the data in the lower position possible (if you have one unaligned byte, write it to bits 0-7 of the data register). Remember that the data register's endianness depends upon the "Big Endian" bit in the MAC Control register.

  6. Once the data has been written, set the "End of Frame" bit.

Receiving Data from the 802.11 Core (Receiving)

Receiving

  1. If the "Frame Ready" bit in the "RX Control" register is not set
    1. return since the data can't be received yet
  2. Write the "Frame Ready" bit to the "RX Control" register
  3. Wait until the "Data Ready" bit is set in the "RX Control" register (check it every 10uS for 100uS). If the "Data Ready" bit is never set, return
  4. RX Header
  5. Data - Remember that the data register's endianness depends upon the "Big Endian" bit in the MAC Control register.

  6. If this is PIO Queue 3

Receiving Error

If an error occurs during the receiving process, flush the received frame by writing the "Data Ready" bit to to the "RX Control" register.


Exported/Archived from the wiki to HTML on 2016-10-27