SSLPN PHY Code
Call SSLPN PHY Set Chanspec Default Tweaks with argument 1
Call SSLPN PHY Radio Init
Call SSLPN PHY RC Cal
- Write 0x3F to Radio Register 0x55
Call SSLPN PHY Set Chanspec with radio_chanspec as argument
Call SSLPN PHY Set Chanspec Default Tweaks with radio_chanspec as argument
- If PHY Revision is 1
- Loop 101 times from 0 with index i
Set sslpnphy_saved_tx_user_target[i] to txpwr_limit[i]
- If PHY Revision is 1
- Write 0x00C1 to PHY Register 0x570
- Write 0x00FF to PHY Register 0x571
- Write 0xFF1B to PHY Register 0x572
- Write 0xFF39 to PHY Register 0x573
- Write 0x00EC to PHY Register 0x574
- Write 0x0034 to PHY Register 0x575
- Write 0x001F to PHY Register 0x576
- Write 0xFFF7 to PHY Register 0x577
- Write 0xFFF1 to PHY Register 0x578
- Write 0x0100 to PHY Register 0x579
- Write 0x0078 to PHY Register 0x5E0
- Write 0xFFC1 to PHY Register 0x5E1
- Write 0x0100 to PHY Register 0x5E2
- Write 0xFFC1 to PHY Register 0x5E3
- Write 0x0078 to PHY Register 0x5E4
- Write 0xFF7A to PHY Register 0x5E5
- Write 0xFFEE to PHY Register 0x5E6
- Write 0x0000 to PHY Register 0x5E7
- Write 0x0012 to PHY Register 0x5E8
- Write 0x0086 to PHY Register 0x5E9
- Write 0x0041 to PHY Register 0x5EA
- Write 0xFFEC to PHY Register 0x5EB
- Write 0xFF5E to PHY Register 0x5EC
- Write 0x007F to PHY Register 0x5ED
- Write 0x00C8 to PHY Register 0x5EE
- Write 0x0000 to PHY Register 0x5EF
- Write 0x0000 to PHY Register 0x5F0
- Write 0x0000 to PHY Register 0x5F1
- Write 0x0000 to PHY Register 0x5F2
- Write 0x0000 to PHY Register 0x5F3
Else if PHY Revision >= 2
- Write 0x0034 to PHY Register 0x857
- Write 0x001F to PHY Register 0x858
- Write 0xFFF7 to PHY Register 0x859
- Write 0xFFF1 to PHY Register 0x85A
- Write 0x0100 to PHY Register 0x85B
- Write 0x009D to PHY Register 0x852
- Write 0x00ED to PHY Register 0x853
- Write 0xFF19 to PHY Register 0x854
- Write 0xFF48 to PHY Register 0x855
- Write 0x00FF to PHY Register 0x856
- Write 0x0041 to PHY Register 0x5EA
- Write 0x0000 to PHY Register 0x5EF
- Write 0xFFEC to PHY Register 0x5EB
- Write 0x0000 to PHY Register 0x5F0
- Write 0xFF5E to PHY Register 0x5EC
- Write 0x0000 to PHY Register 0x5F1
- Write 0x007F to PHY Register 0x5ED
- Write 0x0000 to PHY Register 0x5F2
- Write 0x00C8 to PHY Register 0x5EE
- Write 0x0000 to PHY Register 0x5F3
- Write 0x0042 to PHY Register 0x5E0
- Write 0x0010 to PHY Register 0x5E1
- Write 0x0100 to PHY Register 0x5E2
- Write 0x0010 to PHY Register 0x5E3
- Write 0x0042 to PHY Register 0x5E4
- Write 0xFF55 to PHY Register 0x5E5
- Write 0xFFB9 to PHY Register 0x5E6
- Write 0x0000 to PHY Register 0x5E7
- Write 0x0047 to PHY Register 0x5E8
- Write 0x00AB to PHY Register 0x5E9
- Write 0x0100 to PHY Register 0x85C
- Write 0x0000 to PHY Register 0x85D
- Write 0x0000 to PHY Register 0x85E
- Write 0x0000 to PHY Register 0x85F
- Write 0x0000 to PHY Register 0x860
- Write 0x002F to PHY Register 0x861
- Write 0x0011 to PHY Register 0x862
- Write 0xFFE5 to PHY Register 0x863
- Write 0xFFEC to PHY Register 0x864
- Write 0x0100 to PHY Register 0x865
- Write 0x0000 to PHY Register 0x866
- Write 0x0000 to PHY Register 0x867
- Write 0x0000 to PHY Register 0x868
- Write 0x0000 to PHY Register 0x869
- Write 0x0000 to PHY Register 0x86A
- Set bit 0x0080 in PHY Register 0x631
- Set bits 0x0022 in PHY Register 0x6DA
- Set bit 0x0040 in PHY Register 0x631
- If the chip ID is 0x5356
- Write 0x063F to PHY Register 0x62C
- Write 0x075F to PHY Register 0x62D
- Write 0x7FFF to PHY Register 0x62E
- Write 0x7FFF to PHY Register 0x62F
Set sslpnphy_noise_samples to 5000
Read Radio Register 0xA5 and save in sslpnphy_logen_buf_1
Read Radio Register 0x8E and save in sslpnphy_local_ovr_2
Read Radio Register 0x94 and save in sslpnphy_local_oval_6
Read Radio Register 0x93 and save in sslpnphy_local_oval_5
Read Radio Register 0xA3 and save in sslpnphy_logen_mixer_1
Call SSLPN PHY Set TX Power by Index with argument 50