N PHY TX Power Index (u8 core, s8 txindex, bool restore)

1. If phyhang_avoid

   1. Call N PHY Carrier Search with TRUE as argument

2. Loop 2 times with index i

   1. If core & (1 << i) is zero

      1. Continue

   2. If txindex < 0

      1. If nphy_txpwrindex[i].index < 0

         1. Continue

      2. If PHY Revision >= 3

         1. MaskSet PHY register 0x8F with mask 0xFEFF and set with nphy_txpwrindex[i].AfectrlOverride

         2. MaskSet PHY register 0xA5 with mask 0xFEFF and set with nphy_txpwrindex[i].AfectrlOverride

      3. Otherwise

         1. MaskSet PHY register 0x8F with mask 0xBFFF and set with nphy_txpwrindex[i].AfectrlOverride

      4. if i is 0

         1. Write nphy_txpwrindex[i].AfeCtrlDacGain to PHY register 0xAA

      5. Otherwise

         1. Write nphy_txpwrindex[i].AfeCtrlDacGain to PHY register 0xAB

      6. Write (0x1D10 + i) to PHY Register 0x72

      7. Write nphy_txpwrindex[i].rad_gain to PHY Register 0x73

      8. Write 0x3C57 to PHY Register 0x72
      9. Read PHY Register 0x73 and store in tmp
      10. If i is 0

          1. Replace tmp with (tmp & 0x00FF) | (nphy_txpwrindex[i].bbmult << 8)

      11. Otherwise

          1. Replace tmp with (tmp & 0xFF00) | (nphy_txpwrindex[i].bbmult)

      12. Write 0x3C57 to PHY Register 0x72
      13. Write tmp to PHY Register 0x73
      14. If restore is true
          1. Write (0x3C50 + 2 * i) to PHY Register 0x72

          2. Write nphy_txpwrindex[i].iqcomp_a to PHY Register 0x73

          3. Write nphy_txpwrindex[i].iqcomp_b to PHY Register 0x73

          4. Write (0x3C55 + i) to PHY Register 0x72

          5. Write nphy_txpwrindex[i].locomp to PHY Register 0x73

          6. Write (0x3C5D + i) to PHY Register 0x72

          7. Write nphy_txpwrindex[i].locomp to PHY Register 0x73

      15. Call N PHY TX Power Control Enable with nphy_txpwrctrl as argument

      16. Set nphy_txpwrindex[i].index_internal to nphy_txpwrindex[i].index_internal_save

   3. Otherwise

      1. If nphy_txpwrindex[i].index < 0

         1. If PHY Revision >= 3

            1. MaskSet PHY Register 0x8F with mask 0xFEFF and set with nphy_txpwrindex[i].AfectrlOverride

            2. MaskSet PHY Register 0xA5 with mask 0xFEFF and set with nphy_txpwrindex[i].AfectrlOverride

         2. Otherwise

            1. Set nphy_txpwrindex[i].AfectrlOverride to the contents of PHY Register 0xA5

         3. If i is 0

            1. Set nphy_txpwrindex[i].AfeCtrlDacGain to the contents of PHY Register 0xAA

         4. Otherwise

            1. Set nphy_txpwrindex[i].AfeCtrlDacGain to the contents of PHY Register 0xAB

         5. Write (0x1D10 + i) to PHY Register 0x72

         6. Set nphy_txpwrindex[i].rad_gain to the contents of PHY Register 0x73

         7. Write 0x3C57 to PHY Register 0x72
         8. Set tmp to the contents of PHY Register 0x73
         9. If i is 0
            1. Right shift tmp by 8

         10. Write (tmp & 0xFF) to nphy_txpwrindex[i].bbmult

         11. Write (0x3C50 + 2 * i) to PHY Register 0x72

         12. Set nphy_txpwrindex[i].iqcomp_a to the contents of PHY Register 0x73

         13. Set nphy_txpwrindex[i].iqcomp_b to the contents of PHY Register 0x73

         14. Write (0x3C55 + i) to PHY Register 0x72

         15. Set nphy_txpwrindex[i].locomp to the contents of PHY Register 0x73

         16. Set nphy_txpwrindex[i].index_internal_save to nphy_txpwrindex[i].index_internal

      2. Save the value of nphy_txpwrctrl

      3. Call N PHY TX Power Control Enable with 0 as argument

      4. If PHY Revision is 1
         1. Set bit 0x20000 in coreflags
      5. If i is 0
         1. Set gain to 0x68C0
      6. Otherwise
         1. Set gain to 0x6CC0
      7. Write (gain + index) to PHY Register 0x72
      8. Read PHY Register 0x73 and save in gain
      9. Read PHY Register 0x74, left shift by 16, or with gain and save in gain (32 bit)

      10. If PHY Revision id >= 3

          1. Set rad to (gain >> 16) & 0x1FFFF

      11. Otherwise

          1. Set rad to (gain >> 16) & 0x1FFF

      12. Set dac to (gain >> 8) & 0x3F

      13. Set bbmult to gain & 0xFF

      14. If PHY Revision >= 3

          1. If i is 0
             1. Set bit 0x0100 in PHY Register 0x8F
          2. Otherwise
             1. Set bit 0x0100 in PHY Register 0xA5
      15. Otherwise
          1. Set bit 0x4000 in PHY Register 0xA5
      16. If i is 0
          1. Write dac to PHY Register 0xAA
      17. Otherwise
          1. Write dac to PHY Register 0xAB
      18. Write (0x1D10 + i) to PHY Register 0x72
      19. Write rad to PHY Register 0x73
      20. Write 0x3C57 to PHY Register 0x72
      21. Read PHY Register 0x73 and save as tmp
      22. Write 0x3C57 to PHY Register 0x72
      23. If i is 0

          1. Write (tmp & 0x00FF) | (bbmult <<8) to PHY Register 0x73

      24. Otherwise

          1. Write ((tmp & 0xFF00) | bbmult to PHY Register 0x73

FIXME - Incomplete

1. If phyhang_avoid

   1. Call N PHY Carrier Search with FALSE as argument