N PHY RX IQ Est (struct nphy_iq_est *est, u16 samps, u8 time, u8 wait)

  1. Write samps to PHY Register 0x12B
  2. Maskset PHY Register 0x12A with mask 0xFF00 and set with time
  3. If wait is not zero
    1. Maskset PHY Register 0x129 with mask 0xFFFD and set with 0x2
  4. Otherwise
    1. Clear bit 0x2 in PHY Register 0x129
  5. Set bit 0x1 in PHY Register 0x129
  6. Spin wait until bit 0x1 of PHY Register is 0. Wait for a maximum of 10,000 usec - test every 10 usec
  7. If the spin loop timed out
    1. Zero est
  8. Otherwise
    1. Read PHY Register 0x12F, left shift by 16, or with PHY Register 0x12E, and save as est->i0_pwr

    2. Read PHY Register 0x131, left shift by 16, or with PHY Register 0x130, and save as est->q0_pwr

    3. Read PHY Register 0x12D, left shift by 16, or with PHY Register 0x12C, and save as est->iq0_prod

    4. Read PHY Register 0x137, left shift by 16, or with PHY Register 0x136, and save as est->i1_pwr

    5. Read PHY Register 0x139, left shift by 16, or with PHY Register 0x138, and save as est->q1_pwr

    6. Read PHY Register 0x135, left shift by 16, or with PHY Register 0x134, and save as est->iq1_prod

802.11/PHY/N/RxIqEst (last edited 2010-01-12 17:10:35 by lwfinger)