N PHY Power Control

TX Power Fix

The txpid values are two values, one for each radio core. They are initialised in the first part of this function and then used starting with the loop over the two values/radio cores.

1. if PHY hang avoidance is enabled, enable staying in carrier search
2. If the SROM Revision less than 4
   1. Use 0x48 as both of the txpid values in the loop below
3. otherwise
   1. (medium freq range, 5100..5499 mhz)

      1. Use the txpid5ga values from the SPROM in the loop below

   2. (low freq range, 4900..5099 mhz)

      1. Use the txpid5gal values from the SPROM in the loop below

   3. (high freq range, 5500.. mhz)

      1. Use the txpid5gah values from the SPROM in the loop below

   4. 2.4 GHz

      1. Use the txpid2g values from the SPROM in the loop below

4. if the PHY rev is >= 3, use 0x28 instead for both values

5. Save txpid[0] in nphy_txpwrindex[0].index_internal and nphy_txpwrindex[0].index_internal_save

6. Save txpid[1] in nphy_txpwrindex[1].index_internal and nphy_txpwrindex[1].index_internal_save

7. Loop over the txpid values using index i

   1. If PHY Revision >= 3

      1. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

         1. Call N PHY IPA Gain Table to get the appropriate gain table

         2. Use txpid[i] as an index in the gain table to get the tx gain
      2. Otherwise
         1. If the band is 5 GHZ
            1. If the PHY Revision is 3
               1. Use txpid[i] as an index in nphy_txpwrctrl_5GHz_txgain_rev3 to get the tx gain
            2. Else if the PHY Revision is 4
               1. Use txpid[i] as an index in nphy_txpwrctrl_5GHz_txgain_rev4 to get the tx gain
            3. Otherwise
               1. Use txpid[i] as an index in nphy_txpwrctrl_5GHz_txgain_rev5 to get the tx gain
         2. Otherwise
            1. Use txpid[i] as an index in nphy_txpwrctrl_txgain_rev3 to get the tx gain
   2. Otherwise
      1. Use txpid[i] as an index in nphy_txpwrctrl_txgain to get the tx gain

   3. the radio gain is the tx gain shifted down by 16, and masked with 0x1ffff (phy rev >= 3) or 0x1fff (phy rev < 3)

   4. the DAC gain is the tx gain shifted down by 8, masked with 0x3f
   5. the BB multiplier is the TX gain masked with 0xff

   6. If the PHY Revision >= 3

      1. set bit 0x100 in PHY regs 0x8f/0xa5 (depending on loop index)
   7. Otherwise
      1. Set bit 0x4000 in PHY Register 0xa5
   8. write the DAC gain to PHY register 0xaa/0xab (depending on loop index)
   9. write 0x1d10 plus the loop index to PHY register 0x72
   10. write the radio gain to PHY register 0x73 (table write!)
   11. write 0x3c57 to PHY reg 0x72, read value from 0x73
   12. for the first loop iteration, put the BB multiplier into the upper 8 bits of the result (lower 8 bits for second iteration)
   13. write 0x3c57 to PHY reg 0x72
   14. write the calculated value to 0x73

   15. If (nphy_ipa2g_on and band is 2 GHz) or (nphy_ipa5g_on and band is 5 GHz)

       1. Read an N PHY Table with ID (26 + i), length 1, offset (576 + txpid[i]), width 32, and power as data

       2. Maskset PHY Register 0x297/0x29b (depending on loop index) with mask 0xe00f and set with (power << 4) Set bit 0x0004 in PHY Register 0x297/0x29b (depending on loop index)

8. clear bits 0x1f in PHY reg 0xbf
9. if PHY hang avoidance is enabled, disable staying in carrier search

Set up TX power control

FIXME!!

Set up TX power control coefficients

1. if PHY hang avoidance is enabled, enable staying in carrier search
2. read 7 16-bit values from the table 15 from offset 80
3. for the table IDs 26 and 27:

   1. for table 26: calculate the I/Q compensation as the first read value & 0x3ff shifted up by 10, and the second read value & 0x3ff

   2. for table 27: do a similar calculation with the third and fourth read values

   3. write the table ID << 10 ored with 128 to PHY reg 0x72

   4. 128 times: write the higher 16 bits of the I/Q compensation to PHY reg 0x74 and the lower 16 bits to 0x73
4. for the table IDs 26 and 27:
   1. the LO compensation I/Q is the upper/lower 8 bits of the fifth (table id 26) or sixth (27) read value

   2. write the table ID << 10 ored with 448 to PHY reg 0x72

   3. 128 times:

      1. for PHY rev < 3: calculate the new LO compensation I/Q values according to the table by multiplying with the table value, adding 128 and then shifting down by 8 (other PHY revs require no calculation)

      2. calculate I << 8 | Q and write zero to 0x74, that value to 0x73

5. if the PHY rev is < 2, write 0xffff to SHM 0x708 and 0x70e

6. if PHY hang avoidance is enabled, disable staying in carrier search

multiplier table

Setting the TX power control type

1. If the control type is non-zero
   1. write the 84-entry adjusted power table (calculated during setup) to both 8-bit hardware tables 26 and 27 at offset 64
   2. if the control type is 1, set, otherwise clear, bits 0x6000 in PHY reg 0x1e7
   3. clear bit 0x4000 in PHY reg 0xa5
   4. if the PHY rev is less than two, set the lower 8 bits of PHY reg 0xdc to 0x40, otherwise 0x3b

   5. if the PHY rev two or higher and the bandwidth is 40 MHz, clear the 20 in 40 MHz I/Q workaround host flag

2. otherwise
   1. set PHY reg 0x72 to 0x6840
   2. write zero to PHY reg 0x73 84 times (this clears the 84-entry table)
   3. repeat the last two steps with 0x6c40 instead of 0x6840
   4. clear bits 0x6000 in PHY register 0x1e7
   5. set bit 0x4000 in PHY reg 0xa5
   6. if the PHY rev is less than two, set the lower 8 bits of PHY reg 0xdc to 0x5a, otherwise 0x53

   7. if the PHY rev two or higher and the bandwidth is 40 MHz, set the 20 in 40 MHz I/Q workaround host flag

get TX gains

The result is the TX GM, PGA, PAD and IPA for each core

1. if TX power control is zero (off)
   1. if PHY hang avoidance is enabled, enable staying in carrier search
   2. read two 16-bit values from table 7 at offset 0x110, the first is for core 0, the second for core 1
   3. if PHY hang avoidance is enabled, disable staying in carrier search

   4. if the PHY rev is >= 3, the masks are

      1. IPA: 0x000f
      2. PAD: 0x00f0
      3. PGA: 0x0f00
      4. TXGM: 0x7000

   5. if the PHY rev is < 3, the masks are

      1. IPA: 0x0003
      2. PAD: 0x000c
      3. PGA: 0x0070
      4. TXGM: 0x0380
2. if TX power control is enabled (chip doing it), then
   1. read the base index from register 0x1ed (core 0) or 0x1ee (core 1)

   2. if the PHY rev is >= 3, use the lower 16 bits of the Init tables at the base index offset, and treat it as above

   3. if the PHY rev is < 2, use the uppwer 16 bits of the Init tables at the base index offset, and treat it as above