When enabling/disabling an N PHY 802.11 core with PHY revision >= 3, the PHY PLL needs to be enabled/disabled.

enabling

1. set bit 0x10000 in the PHY PLL control register
2. wait until bit 0x1000000 is set, delay 100000 us between checks
3. error if that never happens

disabling

1. clear bit 0x10000 in the PHY PLL control register
2. wait until bit 0x1000000 is clear, delay 100000 us between checks
3. error if that never happens