bcm-v4

[Specification

N PHY Chanspec Setup (struct nphy_sfo_cfg *inp, u16 chanspec)

struct nphy_sfo_cfg {

};

  1. Set tmp to PHY Register 0x09 anded with 1
  2. (If chanspec is for 5 GHz) and (tmp is zero)
    1. Set tmp1 to the contents of MMIO Register 0x492
    2. Write (tmp1 | 4) to MMIO Register 0x492
    3. Set bits 0xC000 in PHY Register 0xC01
    4. Write tmp1 to MMIO Register 0x492
    5. Set bit 0x0001 to PHY Register 0x09
  3. Else if (chanspec is NOT for 5 GHz) and (tmp is not zero)
    1. Clear bit 0x0001 in PHY Register 0x09
    2. Set tmp1 to the contents of MMIO Register 0x492
    3. Write (tmp1 | 4) to MMIO Register 0x492
    4. Clear bits 0xC000 in PHY Register 0xC01
    5. Write tmp1 to MMIO Register 0x492
  4. Write inp->PHY_BW1a to PHY Register 0x1CE

  5. Write inp->PHY_BW2 to PHY Register 0x1CF

  6. Write inp->PHY_BW3 to PHY Register 0x1D0

  7. Write inp->PHY_BW4 to PHY Register 0x1D1

  8. Write inp->PHY_BW5 to PHY Register 0x1D2

  9. Write inp->PHY_BW6 to PHY Register 0x1D3

  10. Extract the channel from the chanspec and save as tmp
  11. If the chanspec is for 5 GHz
    1. Set bit 0x0100 in tmp
  12. If the chanspec is for 40 MHz band width
    1. Set bit 0x0200 in tmp
  13. Call PHY BMAC Write Shared Memory with 0xA0, tmp as arguments

  14. If the channel into in radio_chanspec is 14

    1. Call N PHY Classifier with 2, 0 as arguments

    2. Set bit 0x0800 in PHY Register 0xC0A
  15. Otherwise
    1. Call N PHY Classifier with 2, 2 as arguments

    2. If the band in chanspec is 2 GHz
      1. Clear bits 0x840 in PHY Register 0xC0A
  16. If nphy_txpwrctrl is zero

    1. Call N PHY TX Power Fix

  17. If PHY Revision less than 3
    1. Call N PHY LNA Adjust Gain Table

  18. Call N PHY TX LPF BW

  19. If PHY Revision >= 3 and phy_spuravoid is not zero

    1. Set avoid to 0
    2. Set tmp to the channel in chanspec
    3. If the band width in radio_chanspec is not 40 MHz

      1. If (tmp greater than 4 and tmp less than 9) or tmp is 13 or tmp is 14
        1. Set avoid to 1
    4. Otherwise
      1. If nphy_aband_spurwar_en and (tmp is 38 or tmp is 102 or tmp is 118)

        1. If the chip is 0x4716 and the chip package is 9
          1. Set avoid to 0
        2. Otherwise
          1. Set avoid to 1
    5. If phy_spuravoid is 2

      1. Set avoid to 1
    6. Call PMU Spur Avoid with avoid as argument

    7. If the chip ID is 43222, 43224 or 43225
      1. If avoid
        1. Write 0x5341 to MMIO address 0x62E
        2. Write 0x0008 to MMIO address 0x630
      2. Otherwise
        1. Write 0x8889 to MMIO address 0x62E
        2. Write 0x0008 to MMIO address 0x630
    8. If the PHY Revision is 3 or 4
      1. Call PHY BMAC Core PLL Reset

    9. If avoid
      1. Set bit 0x8000 in PHY Register 0x01
    10. Otherwise
      1. Clear bit 0x8000 in PHY Register 0x01
    11. Call N PHY Reset CCA

    12. Set phy_isspuravoid to avoid

  20. Write 0x3830 to PHY Register 0x17E
  21. Call N PHY Spur Workaround


Exported/Archived from the wiki to HTML on 2016-10-27