wlc_nphy_aci(..., u8 enable, int aci_pwr)

1. If aci_state & 2 is not zero

   1. was_active = 1
2. Otherwise
   1. was_active = 0
3. If enable is not zero
   1. If was_active is not zero
      1. return

   2. Set bit 2 in aci_state

   3. Read Radio Register 0x66 and save in nphy_interference_save.radio_2055_core1_rxrf_spc1

   4. Read Radio Register 0x95 and save in nphy_interference_save.radio_2055_core2_rxrf_spc1

   5. Bitwise OR nphy_interference_save.radio_2055_core1_rxrf_spc1 with 2 and write to Radio Register 0x66

   6. Bitwise OR nphy_interference_save.radio_2055_core2_rxrf_spc1 with 2 and write to Radio Register 0x95

   7. Copy nphy_gain_boost to nphy_interference_save.gain_boost

   8. Set nphy_gain_boost to 0

   9. Call N PHY Adjust LNA Gain Table

   10. Read Radio Register 0x71 and save in nphy_interference_save.radio_2055_core1_rxbb_rxcal_ctrl

   11. Read Radio Register 0xA0 and save in nphy_interference_save.radio_2055_core2_rxbb_rxcal_ctrl

   12. Read Radio Register 0x2B and add 0xC

   13. If the result is less than 0x1F
       1. Bitwise OR that result with 0x20 and store in rccal_val
   14. Otherwise
       1. Store 0x3F in rccal_val

   15. Write rccal_val in Radio Register 0x71

   16. Write rccal_val in Radio Register 0xA0

   17. Write nphy_interference_save.overideDigiGain1 to PHY Register 0x153

   18. Write nphy_interference_save.bphy_peak_energy_lo to PHY Register 0xC33

   19. Set bit 0x8 in PHY Register 0x153

   20. MaskSet PHY Register 0x153 with mask 0xFFF8 and set with 0x4

   21. Write 0xC0 to PHY Register 0xC33

   22. Set hpf_code to 5

   23. Read PHY Register 0x20 and save in nphy_interference_save.init_gain_code_core1

   24. Read PHY Register 0x36 and save in nphy_interference_save.init_gain_code_core2

   25. Write 0x1D06 to PHY Register 0x72

   26. Loop 4 times with loop index i

       1. Read PHY Register 0x73 and save in nphy_interference_save.init_gain_table[i]

   27. MaskSet PHY Register 0x20 with mask 0xF07F and set with hpf_code << 7

   28. MaskSet PHY Register 0x36 with mask 0xF07F and set with hpf_code << 7

   29. Write 0x1D6 to PHY Register 0x72

   30. Loop 4 times with loop index i

       1. Write (hpf_code << 8) | 0x7C to PHY Register 0x73

   31. Read PHY Register 0x21 and save in nphy_interference_save.clip1_hi_gain_code_core1

   32. Read PHY Register 0x37 and save in nphy_interference_save.clip1_hi_gain_code_core2

   33. Write 0x10BE to PHY Register 0x21

   34. Write 0x10BE to PHY Register 0x37

   35. Read PHY Register 0x22 and save in nphy_interference_save.clip1_md_gain_code_core1

   36. Read PHY Register 0x38 and save in nphy_interference_save.clip1_md_gain_code_core2

   37. Write 0x101E to PHY Register 0x22

   38. Write 0x101E to PHY Register 0x38

   39. Read PHY Register 0x23 and save in nphy_interference_save.clip1_lo_gain_code_core1

   40. Read PHY Register 0x39 and save in nphy_interference_save.clip1_lo_gain_code_core2

   41. Write 0x203E to PHY Register 0x23

   42. Write 0x203E to PHY Register 0x39

   43. Read PHY Register 0x28 and save in nphy_interference_save.nb_clip_thresh_core1

   44. Read PHY Register 0x41 and save in nphy_interference_save.nb_clip_thresh_core2

   45. Write 0x53 to PHY Register 0x28

   46. Write 0x53 to PHY Register 0x41

   47. Read PHY Register 0x27 and save in nphy_interference_save.w1_clip_thresh_core1

   48. Read PHY Register 0x3D and save in nphy_interference_save.w1_clip_thresh_core2

   49. MaskSet PHY Register 0x27 with mask 0xFFC0 and set with 0x0014

   50. MaskSet PHY Register 0x3D with mask 0xFFC0 and set with 0x0014

   51. Read PHY Register 0x1D and save in nphy_interference_save.cck_compute_gain_info_core1

   52. Read PHY Register 0x33 and save in nphy_interference_save.cck_compute_gain_info_core2

   53. MaskSet PHY Register 0x1D with mask 0xFE1F and set with 0x0080

   54. MaskSet PHY Register 0x33 with mask 0xFE1F and set with 0x0080

   55. Read PHY Register 0x6A and save in nphy_interference_save.energy_drop_timeout_len

   56. Write 0x2 to PHY Register 0x6A

   57. Read PHY Register 0x1D7 and save in nphy_interference_save.crs_threshold2u

   58. Write 0x2078 to PHY Register 0x1D7

   59. N PHY Update ACI Power with argument aci_pwr

4. Otherwise
   1. If was_active is zero
      1. Return

   2. Copy nphy_interference_save.gain_boost to nphy_gain_boost

   3. N PHY Adjust LNA Gain Table

   4. Write nphy_interference_save.radio_2055_core1_rxrf_spc1 to Radio Register 0x66

   5. Write nphy_interference_save.radio_2055_core2_rxrf_spc1 to Radio Register 0x95

   6. Write nphy_interference_save.radio_2055_core1_rxbb_rxcal_ctrl to Radio Register 0x71

   7. Write nphy_interference_save.radio_2055_core2_rxbb_rxcal_ctrl to Radio Register 0xA0

   8. Write nphy_interference_save.overideDigiGain1 to PHY Register 0x153

   9. Write nphy_interference_save.bphy_peak_energy_lo to PHY Register 0xC33

   10. Write nphy_interference_save.init_gain_code_core1 to PHY Register 0x20

   11. Write nphy_interference_save.init_gain_code_core2 to PHY Register 0x36

   12. Write 0x1D06 to PHY Register 0x73

   13. Loop 4 times with index i

       1. Write nphy_interference_save.init_gain_table[i] to PHY Register 0x73

   14. Write nphy_interference_save.clip1_hi_gain_code_core1 to PHY Register 0x21

   15. Write nphy_interference_save.clip1_hi_gain_code_core2 to PHY Register 0x37

   16. Write nphy_interference_save.clip1_md_gain_code_core1 to PHY Register 0x22

   17. Write nphy_interference_save.clip1_md_gain_code_core2 to PHY Register 0x38

   18. Write nphy_interference_save.clip1_lo_gain_code_core1 to PHY Register 0x23

   19. Write nphy_interference_save.clip1_lo_gain_code_core2 to PHY Register 0x39

   20. Write nphy_interference_save.nb_clip_thresh_core1 to PHY Register 0x2B

   21. Write nphy_interference_save.nb_clip_thresh_core2 to PHY Register 0x41

   22. Write nphy_interference_save.w1_clip_thresh_core1 to PHY Register 0x27

   23. Write nphy_interference_save.w1_clip_thresh_core2 to PHY Register 0x3D

   24. Write nphy_interference_save.cck_compute_gain_info_core1 to PHY Register 0x1D

   25. Write nphy_interference_save.cck_compute_gain_info_core2 to PHY Register 0x33

   26. Write nphy_interference_save.energy_drop_timeout_len to PHY Register 0x6A

   27. Write nphy_interference_save.crs_threshold2u to PHY Register 0x1D7