LP PHY TX Power Control Init
(5.10.56.46 version)
- Create an LP PHY table with width = 32, PHY width = 32. length = 1, and offset = 0
- Establish a lpphy_txgains struct called gains
If this device has hardware power control (Board flags & 0x10000 == 0)
- If the band is 2GHz
- Set gains.gm_gain to 4
- Set gains.pga_gain to 12
- Set gains.pad_gain to 12
- Otherwise
- Set gains.gm_gain to 7
- Set gains.pga_gain to 15
- Set gains.pad_gain to 14
- Set bbmult to 150
- Set gains.dac_gain to 0
Call LP PHY Set TX Gain with gains as argument
Call LP PHY Set BBMult with bbmult as argument
- If the band is 2GHz
- Otherwise
- If the PHY revision is less than 2
- Set the table ID to 10
- Otherwise
- Set the table ID to 7
- Set the table data pointer to integer "ind"
- Loop on ind from 0 to 63 (inclusive) in steps of 1
- Increment the table offset
MaskSet PHY Register 0x4A5 with mask 0xFF00 and set with 0xFF
MaskSet PHY Register 0x4A5 with mask 0x8FFF and set with 0x5000
MaskSet PHY Register 0x4A6 with mask 0xFFC0 and set with 0x1F
- If the PHY revision is less than 2
- If the PHY revision is 1
- Maskset PHY Register 0x43F with mask 0xFFF8 and set with 0x4
Bitwise AND PHY Register 0x448 with mask 0xEFFF
Bitwise OR PHY Register 0x448 with 0x2000
- If the PHY revision is 1
- Otherwise
Bitwise AND PHY Register 0x503 with mask 0xFFFE
Bitwise OR PHY Register 0x503 with 4
Bitwise OR PHY Register 0x503 with 0x10
Read Radio Register 0x121, bitwise AND with 0xF3, and bitwise OR with 1
Write the previous result to Radio Register 0x121
Call LP PHY Set TSSI Mux with argument 1
Bitwise OR PHY Register 0x4A6 with 0x8000
- Write 0xA to PHY Register 0x4A8
Bitwise AND PHY Register 0x4A4 with mask 0xFF80
Bitwise AND PHY Register 0x4A5 with mask 0xF8FF
MaskSet PHY Register 0x4A4 with mask 0x1FFF and set with 0x8000
If the PHY revision >= 2
Call LP PHY Set TX Gain Override with argument 1
Bitwise OR PHY Register 0x44C with 0x1000
Bitwise AND PHY Register 0x44D with mask 0xEFFF
- Perform do_dummy_tx(..., 0x1, 0x1)
Read PHY Register 0x4AB and save as tmp
If lpphy_cck_papd_disabled
- Maskset PHY Register 0x4A8 with mask 0xFF00 and set with 0x0600
- Otherwise
- Clear bits 0xFF in PHY Register 0x4A8
- If tmp bitwise ANDed with 0x8000 is not equal to 0
- Bitwise AND tmp with 0xFF, subtract 32, and save as the new value of tmp
MaskSet PHY Register 0x4A6 with mask 0xFFC0 and set with tmp
Bitwise AND PHY Register 0x44C with mask 0xEFFF
Set lpphy_target_tx_freq to 0
Call LP PHY Set TX Power Control with 0xE000 as argument