LP PHY PAPD Cal (struct lpphy_txcalgains *txgains, int mode)

1. Create a lpphy_txgains gains structure
2. If PHY revision less than 2
   1. Return
3. If txgains is not NULL
   1. If the useindex member of txgains is not zero

      1. Call LP PHY Set TX Power by Index with the index member of txgains as argument

   2. Otherwise

      1. Call LP PHY Set TX Gain with the gains member of txgains as argument

4. Call Set Deaf with 0 as argument

5. Perform a LP PHY BTCX Override Enable

6. If PHY Revision is 2

   1. Call LP PHY Set TX Filter BW with 0 as argument

7. Otherwise

   1. MaskSet PHY Register 0x4EA with mask 0xFFF8 and set with 0x0000

8. MaskSet PHY Register 0x4EB with mask 0xFFF8 and set with 0x0003

9. Save Radio Register 0x4C

10. Save Radio Register 0xF3

11. Set bits 0x0003 in Radio Register 0xF3
12. If the current band is 2GHz

    1. MaskSet Radio Register 0x4C with mask 0xFFCF and set with 0x0020

13. Otherwise

    1. MaskSet Radio Register 0x4C with mask 0xFFCF and set with 0x0010

14. Set bit 0x8000 in PHY Register 0x44C

15. Set bit 0x2000 in PHY Register 0x44D

16. Perform a LP PHY Set RX Gain with 0x40000 as the argument

17. Perform a LP PHY Set TRSW Override with (1, 0) as the arguments

18. Set bit 0x0001 in PHY Register 0x43B

19. Bitwise AND PHY Register 0x43C with 0xFFFE

20. Perform a LP PHY Set BB Mult with argument 0x17

21. If mode is 0
    1. Set index to 20
22. Otherwise
    1. Set index to 63

23. Bitwise AND PHY Register 0x4D0 with 0xFFDF

24. Bitwise OR PHY Register 0x4D0 with 0x0008

25. MaskSet PHY Register 0x4D5 with mask 0xFFC0 and set with index

26. Bitwise OR PHY Register 0x4D5 with 0x3F00

27. MaskSet PHY Register 0x4D6 with mask 0xFFF0 and set with 0x0008

28. Read PHY Register 0x4D3 and bitwise AND with 0xFF and save as tmp (u16)

29. Replace tmp with -62 - tmp/2 (?? on a u16)

30. MaskSet PHY Register 0x4D6 with mask 0x00FF and set with tmp << 8

31. If lpphy_papd_slow_cal is not zero

    1. (So far, the only place that this variable is set to non-zero seems to be in in some kind of ioctl. It may be used for debugging. The non-zero branch is left in the specs, but probably should be ignored for the moment.)
    2. Write 0x2000 to PHY Register 0x4D7

    3. MaskSet PHY Register 0x4D3 with mask 0xF0FF and set with 0x0800

    4. MaskSet PHY Register 0x4D9 with mask 0xFF00 and set with 0x007F

    5. Write 0x0200 to PHY Register 0x4D8

    6. MaskSet PHY Register 0x4D9 with mask 0x00FF and set with 0

32. Otherwise
    1. Write 0x0080 to PHY Register 0x4D7

    2. MaskSet PHY Register 0x4D3 with mask 0xFFF0 and set with 0x0000

    3. MaskSet PHY Register 0x4D9 with mask 0xFF00 and set with 0x0020

    4. Write 0x0010 to PHY Register 0x4D8

    5. MaskSet PHY Register 0x4D9 with mask 0x00FF and set with 0

33. If mode is 4

    1. MaskSet PHY Register 0x4D9 with mask 0xFF00 and set with 0x0040

34. Call Set Deaf with argument 0

35. Call Start TX Tone with arguments 3750, 100

36. Set bit 0x0001 in PHY Register 0x4D0
37. Spin Wait for bit 0x0001 to be set in PHY Register 0x4D0. Test every 10 usec with a maximum of 1,000,000 loops (??)
38. If mode is 4

    1. Call LP PHY Set BB Mult with argument 0

39. Otherwise

    1. Call LP PHY Stop TX Tone

    2. Call LP PHY Clear Deaf with argument 0

40. If mode is 0
    1. Read the 32-bit LP PHY table with ID 9, length 1 and offset of index
    2. Loop from 0 to index (non inclusive) in steps of 1
       1. Write the above table with the offset changed to the loop counter value

    3. Call LP PHY Smooth PAPD with arguments (5, 0, 32)

41. Call LP PHY Clear TRSW Override

42. Restore the saved value of Radio Register 0x4C
43. Restore the saved value of Radio Register 0xF3
44. Clear bit 0x0800 in PHY Register 0x44C

45. Call LP PHY RX Gain Override Enable with argument 0

46. Clear bit 0x0001 in PHY Register 0x43B

47. Call Clear Deaf with argument 0