Initalization routine for a B PHY, Revision 5

1. If the Analog Core Revision is 1

   1. OR Radio Register 0x7A with 0x50

2. If the Board Vendor isn't 0x14E4 with a Board Type of 0x416
   1. Loop 31 times, start with offset 0xA8 and value 0x2120

      1. Write the value to the PHY Register offset

      2. Increment the offset and add 0x202 to the value

3. MaskSet PHY Register 0x35 with mask 0xF0FF and set 0x700

4. If this is a 0x2050 Radio

   1. Write 0x667 to PHY Register 0x38

5. If Core Flags has the G Mode Enable flag (0x20000000) set or the PHY Revision is 2 or greater

   1. If this is a 0x2050 Radio

      1. OR Radio Register 0x7A with 0x20

      2. OR Radio Register 0x51 with 0x4

   2. Write 0 to Core Register 0x3E2

   3. OR PHY Register 0x802 with 0x100

   4. OR PHY Register 0x42B with 0x2000

   5. Write 0x186A to PHY Register 0x1C

   6. MaskSet PHY Register 0x13 with mask 0xFF and set 0x1900

   7. MaskSet PHY Register 0x35 with mask 0xFFC0 and set 0x64

   8. MaskSet PHY Register 0x5D with mask 0xFF80 and set 0xA

   9. Write 0 to PHY Register 0x5B

   10. Write 0 to PHY Register 0x5C

6. If "bad frames preemption" is enabled (default off, user controlled)

   1. Turn on bit 12 in PHY Register 0x401

7. If the Analog Core Revision is 1

   1. Write 0xCE00 to PHY Register 0x26

   2. Write 0x3763 to PHY Register 0x21

   3. Write 0x1BC3 to PHY Register 0x22

   4. Write 0x6F9 to PHY Register 0x23

   5. Write 0x37E to PHY Register 0x24

8. Otherwise

   1. Write 0xCC00 to PHY Register 0x26

9. Write 0xC6 to PHY Register 0x30

10. Write 0x3F22 to Core Register 0x3EC

11. If the Analog Core Revision is 1

    1. Write 0x3E1C to PHY Register 0x20

12. Otherwise

    1. Write 0x301C to PHY Register 0x20

13. If the Analog Core Revision is 0

    1. Write 0x3000 to Core Register 0x3E4

14. Back up the current channel
15. Force to channel 7, even if it's not supported
16. If this isn't a 0x2050 Radio

    1. Write 0x80 to Radio Register 0x75

    2. Write 0x81 to Radio Register 0x79

17. Write 0x20 to Radio Register 0x50

18. Write 0x23 to Radio Register 0x50

19. If this is a 0x2050 Radio

    1. Write 0x20 to Radio Register 0x50

    2. Write 0x70 to Radio Register 0x5A

20. Write 0x7B to Radio Register 0x5B

21. Write 0xB0 to Radio Register 0x5C

22. OR Radio Register 0x7A with 0x7

23. Restore the channel

24. Write 0x80 to PHY Register 0x14

25. Write 0xCA to PHY Register 0x32

26. Write 0x88A3 to PHY Register 0x2A

27. Set TX power using the saved attenuation values
28. If this is a 0x2050 Radio

    1. Write 0xD to Radio Register 0x5D

29. MaskSet Core Register 0x3E4 with mask 0xFFC0 and set 0x4