This page contains various things related to the PHY
Contents
PHY Write Limit
- When a limit of 24 successive PHY writes without an intervening read, a read of the PHY version register should be done. Presumably, this flushes some kind of internal write queue.
PHY TX Error
- When bit 0x0800 is set in the interrupt status, a PHY Transmission error is indicated. If the 802.11 core revision is 11 or 12, ignore this error, otherwise report it.
PHY Info
PHY Modes
There are, as everyone knows, 2 different encodings used for wireless LAN, namely CCK and OFDM. Initially, OFDM was used only in the 5 GHz band for 802.11a and CCK for 802.11b in the 2.4 GHz band. Until 802.11g came along, which introduced the higher data rates of OFDM into the 2.4 GHz band.
When Broadcom designed the PHY for the 802.11g standard, they obviously combined an A and a B PHY into the new G PHY. Therefore, the G PHY often has to be treated like a B PHY or an A PHY. In order to determine whether to access the G PHY's internal A or B PHY they introduced a new line into the PHY register address at bit 0x400, which is set to access the A PHY registers. Hence you can, for example, read register 0x400 to get the revision of the internal A PHY. See the registers page.
PHY Reset
Between putting the PHY into reset and taking it out, there must be at least a 150 uSec delay for the PLL to settle
Put PHY Into Reset
- If this is an N PHY and the bandwidth for this channel is 20 MHz
- Set the 20 MHz NPHY bandwidth (0x400000) flag below
- If this is an N PHY and the bandwidth for this channel is 40 MHz
- Set the 40 MHz NPHY bandwidth (0x800000) flag below
Unset the Core Flags Low unused NPHY bandwidth flags (on all cores) and set with the PHY Reset, Clock Control and NPHY bandwidth flags (as given above)
- Delay for 2 uSec
Unset the PHY Reset Flag in Core Flags Low
- Delay for 1 uSec
Unset the Gated Clocks Flag in Core Flags Low
- Delay for 1 uSec
Enable the Analog Core
Take PHY Out of Reset
Unset the PHY Reset flag and set the Force Gated Clocks flag in TM State Low Flags
- Delay for 1 uSec
Unset the Force Gated Clocks flag in TM State Low Flags
- Delay for 1 uSec
PHY Versions
This is the layout of the PHY Version register.
Mask |
Function |
0xF000 |
Analog Type |
0x0F00 |
PHY Type |
0x000F |
PHY Revision (Microcode, later drivers in some places use mask 0x00FF!) |
As discussed above, G PHYs contain different A and B PHYs.
G PHY revision |
contained B PHY revision |
1 |
5 |
2 and higher |
6 |
The contained A PHY revision can be checked in PHY Register 0x400 (i.e. the OFDM PHY Register 0x00).
PHY Types
Value |
Type |
|
0 |
A PHY |
|
1 |
B PHY |
|
2 |
G PHY |
|
3 |
|
|
4 |
N PHY |
|
5 |
LP PHY (Low Power A/B/G) |
|
6 |
SSLPN PHY (Single Stream Low Power N) |
|
7 |
HT PHY (Three Stream N) |
|
8 |
LCN PHY (Single Stream N) |
|
9 |
LCNXN PHY (Two Stream N) |
Software sets type to 4 (N PHY) and increments PHY Revision by 16 |
Analog
Analog Types
FIXME: figure out what this means
Value |
Type |
0 |
|
1 |
11G 018 |
2 |
11G 018 ALL |
3 |
11G 018 ALL I |
4 |
11G 013 |
5 |
11N 013 |
More information on the Analog Core
Table Write
Requires:
- table ID
- table offset
- table width
- data, data length (in words of 'table width')
- table address, data high, data low registers
- For N PHY, address is 0x72, data high is 0x74, data low is 0x73
- For LP PHY and LCN PHY, address is 0x455, data high is 0x457, data low is 0x456
- Newest LP PHY code also needs the PHY width
Operation:
write table ID << 10 | table offset to the table address register
- for each item in the data list, treating the data as a u8/u16/u32 array respectively based on the table width, write the data to the data low register, or if it's 32-bit data to the data high and data low registers
Table Read
Requires:
- table ID
- table offset
- table width
- data length (in words of 'table width')
- table address, data high, data low registers
- For N PHY, address is 0x72, data high is 0x74, data low is 0x73
- For LP PHY and LCN PHY, address is 0x455, data high is 0x457, data low is 0x456
- Newest LP PHY code also needs the PHY width
Returns:
- table data
Operation:
write table ID << 10 | table offset to the table address register
- for each item in the data list, treating the data as a u8/u16/u32 array respectively based on the table width, read the data from the data low register, or if it's 32-bit data from the data high and data low registers