bcm-v4

[Specification

This page contains various things related to the PHY

PHY Write Limit

PHY TX Error

PHY Info

PHY Modes

There are, as everyone knows, 2 different encodings used for wireless LAN, namely CCK and OFDM. Initially, OFDM was used only in the 5 GHz band for 802.11a and CCK for 802.11b in the 2.4 GHz band. Until 802.11g came along, which introduced the higher data rates of OFDM into the 2.4 GHz band.

When Broadcom designed the PHY for the 802.11g standard, they obviously combined an A and a B PHY into the new G PHY. Therefore, the G PHY often has to be treated like a B PHY or an A PHY. In order to determine whether to access the G PHY's internal A or B PHY they introduced a new line into the PHY register address at bit 0x400, which is set to access the A PHY registers. Hence you can, for example, read register 0x400 to get the revision of the internal A PHY. See the registers page.

PHY Reset

Between putting the PHY into reset and taking it out, there must be at least a 150 uSec delay for the PLL to settle

Put PHY Into Reset

  1. If this is an N PHY and the bandwidth for this channel is 20 MHz
    1. Set the 20 MHz NPHY bandwidth (0x400000) flag below
  2. If this is an N PHY and the bandwidth for this channel is 40 MHz
    1. Set the 40 MHz NPHY bandwidth (0x800000) flag below
  3. Unset the Core Flags Low unused NPHY bandwidth flags (on all cores) and set with the PHY Reset, Clock Control and NPHY bandwidth flags (as given above)

  4. Delay for 2 uSec
  5. Unset the PHY Reset Flag in Core Flags Low

  6. Delay for 1 uSec
  7. Unset the Gated Clocks Flag in Core Flags Low

  8. Delay for 1 uSec
  9. Enable the Analog Core

Take PHY Out of Reset

  1. Unset the PHY Reset flag and set the Force Gated Clocks flag in TM State Low Flags

  2. Delay for 1 uSec
  3. Unset the Force Gated Clocks flag in TM State Low Flags

  4. Delay for 1 uSec

PHY Versions

This is the layout of the PHY Version register.

Mask

Function

0xF000

Analog Type

0x0F00

PHY Type

0x000F

PHY Revision (Microcode, later drivers in some places use mask 0x00FF!)

As discussed above, G PHYs contain different A and B PHYs.

G PHY revision

contained B PHY revision

1

5

2 and higher

6

The contained A PHY revision can be checked in PHY Register 0x400 (i.e. the OFDM PHY Register 0x00).

PHY Types

Value

Type

0

A PHY

1

B PHY

2

G PHY

3

4

N PHY

5

LP PHY (Low Power A/B/G)

6

SSLPN PHY (Single Stream Low Power N)

7

HT PHY (Three Stream N)

8

LCN PHY (Single Stream N)

9

LCNXN PHY (Two Stream N)

Software sets type to 4 (N PHY) and increments PHY Revision by 16

Analog

Analog Types

FIXME: figure out what this means

Value

Type

0

1

11G 018

2

11G 018 ALL

3

11G 018 ALL I

4

11G 013

5

11N 013

More information on the Analog Core

Table Write

Requires:

Operation:

Table Read

Requires:

Returns:

Operation:


Exported/Archived from the wiki to HTML on 2016-10-27