• 802.11
• PHY

This page contains various things related to the PHY

PHY Info

• Registers

• Attach Step

• Initialization

• Initial Calibration and Initialization

• Power Control

• A PHY

• G PHY

• N PHY

• SSLP N PHY

• LP PHY

• Estimate Output Power

• Measure PHY Noise

• Synthetic Pull-Up Workaround

PHY Modes

There are, as everyone knows, 2 different encodings used for wireless LAN, namely CCK and OFDM. Initially, OFDM was used only in the 5 GHz band for 802.11a and CCK for 802.11b in the 2.4 GHz band. Until 802.11g came along, which introduced the higher data rates of OFDM into the 2.4 GHz band.

When Broadcom designed the PHY for the 802.11g standard, they obviously combined an A and a B PHY into the new G PHY. Therefore, the G PHY often has to be treated like a B PHY or an A PHY. In order to determine whether to access the G PHY's internal A or B PHY they introduced a new line into the PHY register address at bit 0x400, which is set to access the A PHY registers. Hence you can, for example, read register 0x400 to get the revision of the internal A PHY. See the registers page.

PHY Reset

Between putting the PHY into reset and taking it out, there must be at least a 150 uSec delay for the PLL to settle

Put PHY Into Reset

1. If this is an N PHY and the bandwidth for this channel is 20 MHz
   1. Set the 20 MHz NPHY bandwidth (0x400000) flag below
2. If this is an N PHY and the bandwidth for this channel is 40 MHz
   1. Set the 40 MHz NPHY bandwidth (0x800000) flag below

3. Unset the Core Flags Low unused NPHY bandwidth flags (on all cores) and set with the PHY Reset, Clock Control and NPHY bandwidth flags (as given above)

4. Delay for 2 uSec

5. Unset the PHY Reset Flag in Core Flags Low

6. Delay for 1 uSec

7. Unset the Gated Clocks Flag in Core Flags Low

8. Delay for 1 uSec

9. Enable the Analog Core

Take PHY Out of Reset

1. Unset the PHY Reset flag and set the Force Gated Clocks flag in TM State Low Flags

2. Delay for 1 uSec

3. Unset the Force Gated Clocks flag in TM State Low Flags

4. Delay for 1 uSec

PHY Versions

This is the layout of the PHY Version register.

As discussed above, G PHYs contain different A and B PHYs.

The contained A PHY revision can be checked in PHY Register 0x400 (i.e. the OFDM PHY Register 0x00).

PHY Types

Analog

Analog Types

FIXME: figure out what this means

More information on the Analog Core

Table Write

Requires:

• table ID
• table offset
• table width
• data, data length (in words of 'table width')
• table address, data high, data low registers
• For N PHY, address is 0x72, data high is 0x74, data low is 0x73
• For LP PHY, address is 0x455, data high is 0x457, data low is 0x456

Operation:

• write table ID << 10 | table offset to the table address register

• for each item in the data list, treating the data as a u8/u16/u32 array respectively based on the table width, write the data to the data low register, or if it's 32-bit data to the data high and data low registers

Table Read

Requires:

• table ID
• table offset
• table width
• data length (in words of 'table width')
• table address, data high, data low registers
• For N PHY, address is 0x72, data high is 0x74, data low is 0x73
• For LP PHY, address is 0x455, data high is 0x457, data low is 0x456

Returns:

• table data

Operation:

• write table ID << 10 | table offset to the table address register

• for each item in the data list, treating the data as a u8/u16/u32 array respectively based on the table width, read the data from the data low register, or if it's 32-bit data from the data high and data low registers