This page describes the instruction format for the microcode in core revisions 5 and higher. 4 and lower use a different format.

general

The processor always works on 16-bit words. Hence, all memory addressing is also done in 16-bit quantities (except for jumps, which are done in instruction numbers or 8-byte quantities). For example, to write to the shared memory at byte offset 0x002 you have to write to 0x001 from the microcode.

The processor works completely in little endian.

instruction format

We write instructions as

ooo  Xxx yyy zzz

with each character indicating 4 bits, while the actual instruction in binary is then

xxyyyzzz0000oooX

if you treat the firmware as 32-bit values converted to big endian. If you treat it as 64-bit values and then convert to big endian, it becomes easier:

0000oooxxxyyyzzz

Core revisions 15 and up use yet a new microcode format. It uses the same instructions, but each operand has 13 instead of twelve bits, in 64-bit big endian again (this time each character being a bit):

0000000000000ooooooooooooXxxxxxxxxxxxxYyyyyyyyyyyyyZzzzzzzzzzzzz

Also, some instructions are written in the same way as

ooo  Xxx yyy jjj

or

ooo  Aaa bbb ccc

Which will be explained in more detail with the instruction. If nothing else is mentioned, xxx, yyy and zzz always denote regular operands as below.

operands

For core revision 5 to 14 the operands look like this.

xxx is (binary)

result

0b0mmm mmmm mmmm

m is a memory (shm) address (you can only use one as input per instruction)

0b100. .... ....

register access (you can only use one as input per instruction)

0b101r rroo oooo, 0 <= r <= 6

memory at oooooo + Base r

0b1011 10.. ....

(does not exist?)

0b1011 11rr rrrr

CPU register r

0b11ii iiii iiii

i is a 10-bit signed immediate (sign extended to 16 bits before operating with)

For core revisions 15 and up, the prefixes are the same but the variable part is longer although it's not sure whether there really are more registers and more memory.

xxx is (binary)

result

0b0mmmm mmmm mmmm

m is a memory (shm) address (you can only use one as input per instruction)

0b100.. .... ....

register access (you can only use one as input per instruction)

0b101rr rooo oooo

memory at ooooooo + Base r

0b10111 0... ....

(does not exist?)

0b10111 1rrr rrrr

CPU register r

0b11iii iiii iiii

i is a 11-bit signed immediate (sign extended to 16 bits before operating with)

instructions

arithmetic

add

1cL  xxx yyy zzz

zzz := xxx + yyy + (carry if applicable)

L can have values ORed from the following:

mask

meaning

0x1

use carry bit

0x2

set carry bit

This is not the same as the one for sub.

sub

1dL  xxx yyy zzz

zzz := xxx - yyy - (carry if applicable)

L can have values ORed from the following:

mask

meaning

0x1

use carry bit

0x2

set carry bit

This is not the same as the one for add.

multiply (rev 11+ only)

101  xxx yyy zzz

zzz := (xxx * yyy) >> 16
IHR[06d] := xxx * yyy

arithmetic right shift

130  xxx yyy zzz

zzz := xxx >> yyy (filling up with the sign bit)

logical

or

160  xxx yyy zzz

zzz := xxx | yyy

and

140  xxx yyy zzz

zzz := xxx & yyy

xor

170  xxx yyy zzz

zzz := xxx ^ yyy

logical right shift

120  xxx yyy zzz

zzz := xxx >> yyy

left shift

110  xxx yyy zzz

zzz := xxx << yyy

shift right over two registers

2MS  xxx yyy zzz

mask := 1<<(M+1) - 1
tmp  := (yyy<<16) | xxx
zzz  := (tmp >> S) & mask

rotate left

1a0  xxx yyy zzz

zzz := (xxx << yyy) | (xxx >> (16-yyy))

rotate right

1b0  xxx yyy zzz

zzz := (xxx >> yyy) | (xxx << (16-yyy))

clear bits

150  xxx yyy zzz

zzz := xxx & (~yyy)

or with shift and select

3MS  xxx yyy zzz

mask := 1<<(M+1) - 1
mask := (mask << S) | (mask >> (16-S))
tmp  := (xxx << S) | (xxx >> (16-S))
zzz  := (tmp & mask) | (yyy & ~mask)

jumps

All but the special jumps can have their meaning inverted by setting the lowest bit, i.e. jump if less or equal is implemented as jump if not bigger, hence 0d5 or 0dd.

jump if binary and

040  xxx yyy jjj

if (xxx & yyy)
    pc := jjj

jump if all bits set

050  xxx yyy jjj

Every bit set in x needs to be set in y.