The host flags are a combined 80 bit register with the following flags:
Mask |
Meaning |
Default/Notes |
0x00000000000000000001 |
uCode Antenna diversity help |
enabled/disabled when setting antenna diversity |
0x00000000000000000002 |
SYM workaround |
on for G PHY |
0x00000000000000000004 |
Receive pullup workaround |
off |
0x00000000000000000008 |
4 dB CCK power boost (exclusive PA gain OFDM boost) |
on for G PHY rev < 3 unless OFDM power boost is enabled |
0x00000000000000000010 |
Bluetooth Coexistence |
? |
0x00000000000000000020 |
Enable g-mode DC canceller filter bw workaround |
on for G PHY revision 1 |
0x00000000000000000040 |
Enable PA gain OFDM boost |
on for G PHY if BFL_PACTRL is set |
0x00000000000000000080 |
Enable ACPR. Disable for Japan, channel 14 |
enabled/disabled when setting channel |
0x00000000000000000100 |
Enable EDCF (core revision > 4 only) |
on if WME, must be set while MAC suspended |
0x00000000000000000200 |
TSSI reset PSM ucode workaround |
off? |
0x00000000000000000400 |
disable slow clock request in uCode |
on for multifunction boards (boardflag NO-PLL-DOWN set) |
0x00000000000000000800 |
Enable ACI workaround: shift bits by 2 on PHY CRS |
enabled disabled during G PHY ACI |
0x00000000000000001000 |
2060 radio workaround, causes uCode to inform 2060 radio off rx/tx/rx transitions |
enabled during A PHY setup |
0x00000000000000002000 |
radar workaround |
off? |
0x00000000000000004000 |
enable use of default keys, see Crypto Engine |
N/A |
0x00000000000000008000 |
afterburner enabled |
on? |
0x00000000000000010000 |
Bluetooth 4-priority coexistance |
off? |
0x00000000000000020000 |
fast wake-up uCode |
off? |
0x00000000000000040000 |
force VCO recalculation when powering up synthpu |
on for 2050 radio revision < 6 |
0x00000000000000080000 |
PCI slow clock workaround |
on if connected via PCI and PCI core revision is <= 10 (related to Power Save Mode as well) |
0x00000000000000100000 |
Skip Adjust TSF |
Do not update TSF when receiving beacons or probe responses |
0x00000000000000200000 |
4318 TSSI |
off? |
0x00000000000000400000 |
flush broadcast/multicast FIFO immediately |
N/A |
0x00000000000000800000 |
enable hardware power control |
enabled during TX power SHM update |
0x00000000000001000000 |
Bluetooth coexistence in alternate pins |
? |
0x00000000000002000000 |
enable bluetooth check during transmission |
off? |
0x00000000000004000000 |
skip CFP update |
enable during scan on other channels |
0x00000000000008000000 |
NPHY 40 MHz WAR |
|
0x00000000000010000000 |
ANT SEL EN |
enable antenna selection (ucode rev <= 12) |
0x00000000000020000000 |
ANT SEL MODE |
antenna selection mode (ucode rev <= 12) |
0x00000000000100000000 |
MIMO Antenna selection enabled |
(ucode rev >= 13) |
0x00000000000200000000 |
Antenna selection mode |
0 - 2x3, 1 - 2x4 (ucode rev >= 13) |
0x00000000000400000000 |
Reserved |
|
0x00000000000800000000 |
Reserved |
|
0x00000000001000000000 |
N PHY MLADV workaround |
|
0x00000080000000000000 |
Force CCK TX on core 0 |
board level war |
0x00004000000000000000 |
EXT PA Enable |
for 4313A0 boards |
0x00010000000000000000 |
4313 GPIO Control |
|
0x00020000000000000000 |
Reserved |
|
0x00040000000000000000 |
Reserved |
|
The following ones are probably only valid for revision 13 microcode and higher (addition of the N PHY).
Mask |
Meaning |
Default/Notes |
0x00000000000000000200 |
20 in 40 MHz I/Q workaround |
on for N PHY rev < 2 (new meaning for 0x200 bit on new ucode) |
0x00000000000008000000 |
N PHY 40 MHz workaround |
on for N PHY rev < 2 |
0x00000000000020000000 |
Bluetooth 3-wire coexistence |
new meaning on new ucode? |
0x00000000000040000000 |
Bluetooth coexistence (antenna mode) |
? |
0x00000000000400000000 |
Bluetooth coexistence related |
|
0x00000000000800000000 |
Bluetooth coexistence related |
|
0x00000000001000000000 |
N PHY ML ADV workaround |
|
0x00000000002000000000 |
IBSS decryption mode |
|
0x00000000010000000000 |
3 Wire BTCX RESP |
Allow responce during BT |
0x00000000020000000000 |
BTCX PS PROT |
corerev >= 13 BT Coexistence |
0x00000000040000000000 |
3 Wire BTCX RSP LOW |
Reduce response power if BT is active |
0x00000000080000000000 |
PR 45960 workaround |
|
Influence on microcode
based on microcode version 323.100
radar workaround
Causes the microcode to modify the Radar Threshold 1 A PHY register (uses the value 0x3d8 or SHM Radar Register value).
Receive pullup workaround
Causes the microcode to set the bits 0xc000 to 0x8000 for 40 cycles (and then reset them to 0) every 16 microseconds.
Bluetooth coexistence
Depending on various other things, signalling on GPIOs.
hardware power control
Sometimes sets bits 0xFC00 of the PHY TX Control Word to the entry in word 7 of some SHM table (A PHY: 0x320, others: 0x370)
- for each transmission (after or before?) adjust the RSSI Filter B0 or Power Base Index PHY Register depending on the current value of the TX estimated power register and the SHM TX Power Target/Max/... values.
Enable EDCF
Causes the Microcode to use multiple FIFOs and keep track of the various timers for the EDCF, need to read up on that and try to understand what exactly it does.
flush broadcast/multicast FIFO immediately
Not sure, causes it to pull data from FIFO 5 maybe? Various SHM values have influence, like the Last posted Frame ID to the broadcast/multicast FIFO, also checks Hostflag 0x000000100000!
4318 TSSI
Sets the GPHY Analog Override Register to 0/8 (on TX/RX? RX/TX? other spots?)
Afterburner
Too long to explain here. "125Mbps" Broadcom markets is Afterburner, which really is frame aggregation similar to what 802.11N defines. Also influences slot timing and possibly more parameters.
FIXME: is it really frame aggregation or block ack (defined in 802.11e?)
TSSI reset PSM ucode workaround
Set TX Control 0 Radio register to 0x11/0x31 on some transmissions (which?)
Enable PA gain OFDM boost
Deassert GPIO 9 when transmitting OFDM frames, also modify Power Control Radio Register writing the value OFDM offset + Radio Power (both from SHM.)
Enable ACI workaround
Modify A PHY N1/N2 Threshold register sometimes.
enable use of default keys
Explained on the crypto page.
skip CFP update
Skips some code doing NAV/TSF (probably CFP) changes.
PCI slow clock workaround
wait 20 microseconds before entering sleep (powersave)
disable slow clock request in uCode
Do not use the SCC timer for waking up from sleep (powersave), ...
fast wake-up uCode
Program a different wakeup time for sleep
antenna diversity
Switch antenna automatically (based on what?)
SYM workaround
For some frames (data, special PLCP length or something, ...) change IFS control.
4 dB CCK power boost
???? Seems to only do similar things to the OFDM power boost?
Enable ACPR
Set TX Control 1 Radio register to 4 or 0 depending on some other factors.