• 802.11
• Host Flags

The host flags are a combined 32 bit register with the following flags:

The following ones are probably only valid for revision 13 microcode and higher (addition of the N PHY).

Influence on microcode

based on microcode version 323.100

radar workaround

Causes the microcode to modify the Radar Threshold 1 A PHY register (uses the value 0x3d8 or SHM Radar Register value).

Receive pullup workaround

Causes the microcode to set the bits 0xc000 to 0x8000 for 40 cycles (and then reset them to 0) every 16 microseconds.

Bluetooth coexistence

Depending on various other things, signalling on GPIOs.

hardware power control

• Sometimes sets bits 0xFC00 of the PHY TX Control Word to the entry in word 7 of some SHM table (A PHY: 0x320, others: 0x370)

• for each transmission (after or before?) adjust the RSSI Filter B0 or Power Base Index PHY Register depending on the current value of the TX estimated power register and the SHM TX Power Target/Max/... values.

Enable EDCF

Causes the Microcode to use multiple FIFOs and keep track of the various timers for the EDCF, need to read up on that and try to understand what exactly it does.

flush broadcast/multicast FIFO immediately

Not sure, causes it to pull data from FIFO 5 maybe? Various SHM values have influence, like the Last posted Frame ID to the broadcast/multicast FIFO, also checks Hostflag 0x000000100000!

4318 TSSI

Sets the GPHY Analog Override Register to 0/8 (on TX/RX? RX/TX? other spots?)

Afterburner

Too long to explain here. "125Mbps" Broadcom markets is Afterburner, which really is frame aggregation similar to what 802.11N defines. Also influences slot timing and possibly more parameters.

FIXME: is it really frame aggregation or block ack (defined in 802.11e?)

TSSI reset PSM ucode workaround

Set TX Control 0 Radio register to 0x11/0x31 on some transmissions (which?)

Enable PA gain OFDM boost

Deassert GPIO 9 when transmitting OFDM frames, also modify Power Control Radio Register writing the value OFDM offset + Radio Power (both from SHM.)

Enable ACI workaround

Modify A PHY N1/N2 Threshold register sometimes.

enable use of default keys

Explained on the crypto page.

skip CFP update

Skips some code doing NAV/TSF (probably CFP) changes.

PCI slow clock workaround

wait 20 microseconds before entering sleep (powersave)

disable slow clock request in uCode

Do not use the SCC timer for waking up from sleep (powersave), ...

fast wake-up uCode

Program a different wakeup time for sleep

antenna diversity

Switch antenna automatically (based on what?)

SYM workaround

For some frames (data, special PLCP length or something, ...) change IFS control.

4 dB CCK power boost

???? Seems to only do similar things to the OFDM power boost?

Enable ACPR

Set TX Control 1 Radio register to 4 or 0 depending on some other factors.