This ensures that the chip is working, memory accesses work and side effects trigger correctly.
- Backup the 32 bit contents of shared memory word 0.
- Write the value 0x55aaaa55 to that shared memory location and read it back to test for endianness problems.
- repeat with 0xaa5555aa.
- restore the original value
- for core revisions 3 through 10:
write 0xAAAA as a 16-bit value to the usually 32-bit register "TSF Contention Free Period Start" (0x18c)
- write the 32-bit value 0xccccbbbb to the same register
verify that 0xcccc and 0xbbbb are read back from the "TSF CFP Start High"/Low registers (0x604, 0x606), the 32-bit register shadows these two 16-bit registers but with update side effects
clear TSF CFP start (0x18c)
- validate that MAC control has bit "IHR Region Enabled" and possibly "G Mode" set.