Contents

  1. Analog Core Revision
  2. Enable / Disable the Analog Core
    1. A / B / G / LP PHYs
    2. N PHYs

Analog Core Revision

The Analog Core revision is a component of the PHY Versioning register (0x3E0)

Enable / Disable the Analog Core

A / B / G / LP PHYs

To enable the Analog Core, write 0 to Core Register 0x3E6

To disable the Analog Core, write 0xF4 to Core Register 0x3E6

N PHYs

To enable the Analog Core, write 0 to PHY Register 0xA5

To disable the Analog Core, write 0x7FFF to PHY Register 0xA5

802.11/Analog (last edited 2007-10-28 22:49:21 by localhost)